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Executing a Store instruction

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We now examine in detail how the basic pipeline CPU executes the store instruction.

• Store instruction format
  • Our pipelined CPU supports 2 types of store instruction formats:

    str r1, [r2 + r3]: Stores the value in register R1 to memory at address (location) given by R2+R3 (R1 is given by the destination register. R2 is given by the source operand 1 and R3 is given by the source operande 2) str r1, [r2 + #N]: Store the value in register R1 to memory at address (location) given by R2+N (N is a constant) (R1 is given by the destination register. R2 is given by the source operand 1 and N is given by the source operande 2)

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• Store Instruction Encoding
  • Refer back to this webpage on how Aaron Bush represents the STORE instruction formats: click here

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  • Example 1: str r1, [r2 + r3] (Memory[R1 + R2] := R3)

    The instruction is encoded as follows:

    STORE ------- Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ OpCode P: (1 update PSR, 0 do not) ----------------------- I: (1 use Src 2 as constant, 0 reg num) 0 0 Add 0 1 Subtract 1 0 AND 1 1 OR

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  • Example 2: str r1, [r2 + 3] (Memory[R2 + 3] := R1)

    The instruction is encoded as follows:

    STORE ------- Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ OpCode P: (1 update PSR, 0 do not) ----------------------- I: (1 use Src 2 as constant, 0 reg num) 0 0 Add 0 1 Subtract 1 0 AND 1 1 OR

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• How is the store instruction executed
  • Example:

    str r1, [r2 + r3] (Store data from reg R1 to memory addr R2+R3)

    Execution:

    Fetch the operands: Fetch the value of source operand 1 (= R2) into the "A"-register Fetch the value of source operand 2 (= R3) into the "B"-register (We will also fetch the constant opeand from source operand 2 into the IR1 register) Fetch the value of destination operand (= R1) into the "D"-register Compute the memory address: Add: R2 + R3           Update (write) the memory location: Send: R2 + R3 on the address bus (and give MEMREQ and WRITE signal to memory) Send: R1 on the data bus (this value is stored in SMDR !!!!) (That's all we need to do. The memory will be updated with the value on the databus)

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  Slideshow:

  

  (Meaning of bits in STORE instruction code)

  

  (Cycle 1: fetch ALU instruction in ID stage)

  

  (Start of cycle 2: ID stage fetch operands)

  

  (End of cycle 2: operand fetched, instruction advances)

  

  (Start of cycle 3: EX stage obtain and compute on operands)

  

  (End of cycle 3: results stored in ALUo (and DMAR) registers, instruction advances)

  

  (Start of cycle 4: STORE instruction want to access memory)

  

  (Start of cycle 4: IF wants to fetch instruction from memory too !!)

  

  (Start of cylce 4: MEM stage execute LD/ST/Branch instruction - IF stage stalled)

  

  (End of cycle 4: MEM stage updated memory, NOP inserted, instruction advances)

  

  (Start of cylce 5: WB stage updates destination register, "str" instruction does not update registers, but memory !)

  

  (End of cycle 5: WB stage does nothing, instruction discarded )

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• Step 1: Fetch

  • At start of the CPU cycle, the IF stage sends out PC
  • At end of the CPU cycle, the IR(ID) register is updated with the instruction fetched (str r1, [r2+r3])
    

  • The picture above depicts the content of the CPU at end of the first CPU cycle (and the start of the 2nd cycle)

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• Step 2: Decode (fetch operands)
  • At start of the CPU cycle, the ID stage sends out selection signal that selects values from R2 (on A bus), R3 (on B bus) and R1 (on D bus).

  • At end of the CPU cycle, the "A" register is updated with R2, the "B" register is updated with R3 and the "D" register is updated with R1.

    R2 and R3 will be used to compute the address (by adding them together) used by the STORE instruction The value of R1 will be written to the selected memory location selected by R2+R3.

  • Also, at the end of the CPU cycle, the instruction (str r1, [r2+r3]) is moved into IR(EX) and a new instruction is fetched into IR(ID)
    

  • The picture above depicts the content of the CPU at end of the second CPU cycle (and the start of the 3rd cycle) - notice that the address (R2 + R3) has not been computed yet... it will be computed in the next cycle....

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• Step 3: Execute (compute)
  • At start of the CPU cycle, the MUX in the EX stage selects values from the "A" register (= R2) and the "B" register (= R3) for the ALU, and use the ALU opcode to make ALU add the input values

  • At end of the CPU cycle, ALUo and DMAR registers is updated with the value R2+R3 (the memory address) and the SMDR register is updated with the value R1 (= the store data)

  • Also, at the end of the CPU cycle, the instruction (str r1, [r2+r3]) is moved into IR(MEM) and a new instruction is fetched into IR(ID)
    

  • The picture above depicts the content of the CPU at end of the 3rd CPU cycle (and the start of the 4th cycle)

  • Notice that the address (R2+R3) is sent on the address bus and the data (R1) is sent on to the databus !!!

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• Step 4: Memory Access or Branch
  • The MEM stage will now use the system bus to access the memory to perform the store operation

  • Just like in the case in the load operation:

    The IF stage also wants to use the system bus to fetch the next instruction The MEM and IF stage cannot share the system bus. We must give higher priority to the MEM stage

  • Conclusion:

    We must stall the IF stage in step 4 of the execution of the STORE instruction

    

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  • There is the same caveat in the STORE instruction that we saw in the LOAD instruction:

    The IF stage is stalled (= not fetching instruction) and will not fetch the next instruction:

    We use the same solution as in the LOAD instruction:

    We "insert" a (harmless) NOP instruction in the IR(ID) register when the MEM stage wants to used the system bus: (This figure was used to illustrate the LOAD instruction, it also applies when we detects a STORE instruction in the MEM stage - i.e., when we see 10 as the first 2 bits in the instruction)

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  • At end of the CPU cycle, ALUo1 registers is updated with the value R2+R3 (but will not be used)

  • Also, at the end of the CPU cycle, the instruction (str r1, [r2+r3]) is moved into IR(WB) and the NOP instruction is fetched into IR(ID)
    

  • The picture above depicts the content of the CPU at end of the 4rd CPU cycle (and the start of the 5th cycle)

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• Step 5: Update register
  • A STORE instruction does not update any register

    We make sure to filter out (= stop) the clock signal to the registers when a STORE instruction is in the WB-stage !!!

    In other words: a STORE instruction will not update anything in step 5

    (In fact, the STORE instruction is completed in step 4 !!! It wrote the data to the memory in that step !!!)

  • At the end of the CPU cycle, the instruction (str r1, [r2+r3]) is discarded and a new instruction is fetched into IR(ID)

  • Notice that the NOP instruction will proceed through the pipe, since it does no harm, its only effect is that the CPU "run less fast"...