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Instruction encoding

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• Prologue
  • In 2010, the student Aaron Bush implemented this pipelined CPU for his honors thesis project.

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  • He also designed the instruction format.

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• Instruction encoding (to make the discussion more concrete)
  • Fact:

    The CPU manufacturer can design the instruction code for the CPU.... I will basically describe Aaron Bush's code here.

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  • Encoding the different instruction types:

    OpCode +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | x | x | | | | | | | | | | | | | | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ x x Instruction Type --------------------------------------------------------------- 0 0 ALU (2 registers or 1 register,1 constant operand) 0 1 Load (memory) 1 0 Store (memory) 1 1 Branch

    Each instruction type has its own instruction format

    (The instruction format was implemented by Arron Bush in his Honor thesis project)

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• The ALU instruction encoding
  • ALU instruction:

    Syntax: ADD destReg, srcReg1, srcReg2 AND destReg, srcReg1, srcReg2 ADD destReg, srcReg1, const AND destReg, srcReg1, const ... etc Endcoding: Dest Reg OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | D | D | D | P | 0 | | | | S | S | S | R | R | R | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ OpCode P: (1 update PSR, 0 do not update PSR) ----------------------- I: (1 use Src 2 as constant, 0 reg num) 0 0 Add 0 1 Subtract 1 0 AND 1 1 OR

    Example:

    Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ===> R6 = R3 - R2 (and update PSR) Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ===> R6 = R3 - 2 (and do NOT update PSR)

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• The LOAD (LDR) instruction encoding
  • LDR instruction:

    Syntax: LDR destReg, [srcReg1 + srcReg2] LDR destReg, [srcReg1 - srcReg2] LDR destReg, [srcReg1 + constant] LDR destReg, [srcReg1 - constant] ... etc Encoding: Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | D | D | D | x | 0 | Op| Op| x | S | S | S | R | R | R | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ OpCode P: (1 update PSR, 0 do not) ----------------------- I: (1 use Src 2 as constant, 0 reg num) 0 0 Add 0 1 Subtract 1 0 AND 1 1 OR

    Example:

    Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ===> LDR R6, [R3 - R2] (Load content of memory address R3-R2 into reg R6) Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ===> LDR R6, [R3 + #2] (Load content of memory address R3+#2 into reg R6)

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• The STORE (STR) instruction encoding
  • STR instruction:

    Syntax: STR destReg, [srcReg1 + srcReg2] STR destReg, [srcReg1 - srcReg2] STR destReg, [srcReg1 + constant] STR destReg, [srcReg1 - constant] ... etc Encoding: Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | D | D | D | x | x | x | x | | S | S | S | R | R | R | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ OpCode P: (1 update PSR, 0 do not) ----------------------- I: (1 use Src 2 as constant, 0 reg num) 0 0 Add 0 1 Subtract 1 0 AND 1 1 OR

    Example:

    Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ===> STR R6, [R3 - R2] (Store content of reg R6 to memory at address R3-R2) Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ===> STR R6, [R3 + 2] (Store content of reg R6 to memory at address R3+2)

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• The branch instruction encoding
  • Branch instruction:

    Syntax: BRA label BEQ label ... etc Encoding: Branch condition <-------------- branch address -----------> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | B | B | B | | | | | | | | | | | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ B B B Branch condition --------------------------------------------------------------- 0 0 0 Branch always 0 0 1 BEQ 0 1 0 BNE 0 1 1 BLT 1 0 0 BLE 1 0 1 BGT 1 1 0 BGE 1 1 1 not used