The MAKE utility

What is MAKE ?
- The make utility help you manage program compilation by tracking file dependencies
- The make program helps you in your development of large programs by:
  - getting information of file dependencies
  - Checking the UPDATE TIME STAMP of files
- These information allows make to determine which source files of the entire program need to be recompiled
Files dependencies
- When we write a program that consists of multiple program source files, we must compile the source files into an executable program file.
- Example:
  consider a program prog that consists of 3 source files
  The following figure shows the compilation process:
- The following files are involved in making the final program file prog:
  - The object files f1.o, f2.o, and f3.o
  - The source files f1.c, f2.c, and f3.c
- The File Dependencies are as follows:
  - In order to create the file prog , we need to use the files f1.o, f2.o and f3.o
  - In order to create the file f1.o, we need to use the file f1.C
  - In order to create the file f2.o, we need to use the file f2.C
  - In order to create the file f3.o, we need to use the file f3.C
- We say that:
  - the file prog depends on files f1.o, f2.o and f3.o
  - the file f1.o depends on the file f1.C, etc., etc.

Specifying inter-file Dependencies in MAKE

The principle by which MAKE operates is file dependencies

A MAKE dependency file contains one of more of the following dependency definition :

TargetName: depend-file1 depend-file2 .... <TAB> Command 1 (to build "TargetName") <TAB> Command 2 (to build "TargetName") <TAB> Long command 2 to \ <TAB> build "TargetName" ... <TAB> Command N to build "TargetName"

When make is invoked without any argument , it will make the first target in the MAKE dependency file

Example: MAKE (dependency) file:

prog: f1.o f2.o f3.o <TAB> CC -o prog f1.o f2.o f3.o f1.o: f1.C <TAB> CC -c f1.C f2.o: f2.C <TAB> CC -c f2.C f3.o: f3.C <TAB> CC -c f3.C

How to read the Makefile:
- prog: f1.o f2.o f3.o
  File prog depends on the files f1.o f2.o f3.o
- The next line tells Make how to build (make) the file prog from the files f1.o f2.o f3.o, namely:

What can MAKE do for you ?
- Don't leave home without it ! :-)
- The name of the dependency file must be either:
  - Makefile or
  - makefile
  (Makefile is preferred, because the ls command will list the file early)
- Using the Makefile or makefile, the MAKE utility can automatically determine WHICH files need to be re-compiled to make the TargetFile after you modified one or more source files .
  (The MAKE utility does this by checking the time stamps on the source files, the object files, and the target files to determine which source files need to be re-compiled....)
- All you need to do is type:
- Example MAKE dependency file: (RectangleRule with predefined precision): ---
  - MAKE file: RIGHT click here and save as "Makefile" (or "makefile") !!!:
  - Source file 1 - containing RectangleRule_Prec(f, a, b, EPS) : click here
  - Source file 2 - containing RectangleRule(f, a, b, N) : click here
  - Source file 3 - containing the f(x) function: click here
  - Source file 4 - containing the main function: click here
  Save all the files in the same directory and type:
- Show off MAKE: (Show file update + make): ---
  - Edit one of the files, any file, juts pick one
  - After saving the file, type:
  - Make will only compile the updated file.
    After compiling the file, it will link the other object files (that do NOT need re-compiling) into the program rect-rule4

Advanced features of MAKE

Multiple Targets in one Makefile
- Sometimes, you may be developing multiple programs that use a common set of function/subroutine files
- Use the following " trick " (a "virtual" target ) to make multiple targets (TargetName1, TargetName2, ....)
- How the trick works:
  - When you type make, make will try to make the target ALL .
  - This will trigger the making of multiple targets TargetName1 , TargetName2 , ... and so on.
Making a specific target in a multi-target Makefile

The make application can be given a target as parameter.

Recall when make is invoked with any parameter , it will make the first target in the Makefile

You can specify a specific target as argument to MAKE.
Example:

UNIX>> make TargetName1

will make the target FONT color="red"> TargetName1
Custom Makefile name...

OK, I lied... You don't HAVE TO name your makefile Makefile/makefile
But it is a whole lot EASIER if you DO...

If you somehow feel the need/urge to use a different name (for whatever reasons), you can use that Makefile to use in the make command with the -f option
Example:

make -f Any-FileName-as-your-Makefile

Macros in Makefiles

A macro processing system is a text replacement processing system

Make has a built-in Macro system

The MAKE utility allows you do:

Define a symbolic name X to represent a String

Use the symbolic name $(X) to replace $(X) with its defined string

Syntax:

Definition of a macro: MACRO_NAME = any string
Using a defined macro: $(MACRO_NAME)

This expression $(MACRO_NAME) will be replaced by the string in the MACRO_NAME definition

Example:

OBJECTS = f1.o f2.o f3.o COMPILER = CC -g prog: $(OBJECTS) <TAB> $(COMPILER) -o prog $(OBJECTS) f1.o: f1.C <TAB> $(COMPILER) -c f1.C f2.o: f2.C <TAB> $(COMPILER) -c f2.C f3.o: f3.C <TAB> $(COMPILER) -c f3.C

Example: change compile option to optimize speed

OBJECTS = f1.o f2.o f3.o COMPILER = CC -fast prog: $(OBJECTS) <TAB> $(COMPILER) -o prog $(OBJECTS) f1.o: f1.C <TAB> $(COMPILER) -c f1.C f2.o: f2.C <TAB> $(COMPILER) -c f2.C f3.o: f3.C <TAB> $(COMPILER) -c f3.C

Example: change compiler to g++

OBJECTS = f1.o f2.o f3.o COMPILER = g++ -g prog: $(OBJECTS) <TAB> $(COMPILER) -o prog $(OBJECTS) f1.o: f1.C <TAB> $(COMPILER) -c f1.C f2.o: f2.C <TAB> $(COMPILER) -c f2.C f3.o: f3.C <TAB> $(COMPILER) -c f3.C

Special built-in MAKE macros

The following macros are predefined in MAKE:

$@ = the current target
Example usage:

prog: file1.o file2.o file3.o <TAB> CC -o $@ file1.o file2.o file3.o
is equal to: prog: file1.o file2.o file3.o <TAB> CC -o prog file1.o file2.o file3.o

$< = source file (right hand side)
Example usage:

file1.o: file1.C <TAB> CC -c $<
is equal to: file1.o: file1.C <TAB> CC -c file1.C

Special Suffixes and Rules

Often, we use the SAME command to process files of the same suffix

Example:

file1.C is compiled using CC -c file1.C into file file1.o
file2.C is compiled using CC -c file2.C into file file2.o
And so on..

We could write one rule for each source file :

file1.o: file1.C CC -c file1.C file2.o: file2.C CC -c file2.C ...

Alternatively, we can teach Make how to handle files with same file name but different suffixes :

# Tells MAKE that you will be using these special suffixes # to make your own rules. .SUFFIXES: .C .o <-- This define the special suffixes .C.o: CC -c $<
NOTE: You don't really need this rule, because this rule is already defined in the commonly used rule file: /usr/share/lib/make/make.rules MAKE reads this rule file each times it runs....

This rules says that when ever you see a file FILENAME.o, it will depend on the file FILENAME.C.
The way make the file FILENAME.o is: CC -c FILENAME.C

Example .SUFFIX definition: ----------------------------------------

Here is a new MAKE dependency file (that you must save it as "Makefile" (or "makefile")): click here

You will need put this RectangleRule_Prec(f, a, b, EPS) function file in the same directory: click here
And the RectangleRule(f, a, b, N) function file: click here
And the f(x) function: click here
And the driver program: click here

After you have put these files in the same directory, type:

make

Final Notes...

You are not restricted in MAKING programs with compilers; you can make anything....

Here is a Makefile that would make a new library file (archive) when some source files are changed:

.C.o: CC -c $< libMyLib.a: file1.o file2.o file3.o ar -rv $@ file1.o file2.o file3.o