/* multiplexor + demultiplexor */

/* Input switches */
Switch 4a sw0 '0' ZERO;
Switch 3a sw1 '1' ZERO;
Switch 2a sw2 '2' ZERO;
Switch 1a sw3 '3' ZERO;

/* Controls for the mux */
Switch 6a sw4 'a' ZERO;
Not    6a sw4 not_out_a;
Switch 7a sw5 'b' ZERO;
Not    7a sw5 not_out_b;

And 4c sw0 not_out_a not_out_b out_1;
And 3c sw1 not_out_a sw5 out_2;
And 2c sw2 sw4 not_out_b out_3;
And 1c sw3 sw4 sw5 out_4;
Or  3d out_4 out_3 out_2 out_1 mux_out;

/* Controls for the demux */
Switch 6d sw6 'c' ZERO;
Not    6d sw6 not_out_c;
Switch 7d sw7 'd' ZERO;
Not    7d sw7 not_out_d;

And 4f mux_out not_out_c not_out_d final_1;
And 3f mux_out not_out_c sw7 final_2;
And 2f mux_out sw6 not_out_d final_3;
And 1f mux_out sw6 sw7 final_4;

Probe 4g final_1;
Probe 3g final_2;
Probe 2g final_3;
Probe 1g final_4;