---

Associtive Cache and its architecture

---

• Memory organization
  • Programmer's view of the computer memory:

    ---

    ---

  • Fact:

    The data bus of computers nowadays has at least 32 wires In the discussion, I will assume that the databus has 32 bits (wires) Each memory read operation will use all the data bus wires Therefore: Each memory read operation will fetch 4 bytes from memory (I have assumed that the databus has 32 bits !)

    ---

    ---

  • Data transfer view of the computer memory:

    Block number:

    Block number = used to identify a transfer unit in the memory (uniquely !!!)

  ---

  ---

  ---

  ---

• Structure of an Associative Cache
  • Structure of an Associative Cache:

    Meaning of the fields:

    Valid Flag (bit field): 0 = invalid entry (the value in this entry is invalid --- do not use !!!) 1 = valid entry (the value in this entry is valid) Block number: If valid, the block number field contains the block number of the transfer unit in memory Recall: a block number identifies the transfer data unit as follows Value: If valid, the value field contains the value of the corresponding transfer unit in memory

    ---

    ---

  • Example of the content of an Associative cache:

  ---

  ---

  ---

  ---

• Nomenclature
  • Slot:

    Slot = an entry in a cache

  ---

  ---

  ---

  ---

• "Decoding" the information stored in an Associative Cache
  • Example of decoding the information stored in an Associative Cache:

    Consider the highlighted entry: The entry in the slot is valid: The transfer unit is block 4 in memory: Since the entry is valid, the memory must contains the value 567 at that transfer unit:

  ---

  ---

  ---

  ---

• Using the (associative) cache --- with block numbers
  • Suppose the content of an Associatve Cache is:

    ---

  • The CPU now makes a read request for the transfer unit (block id) 103

    Question:

    Is this transfer unit found in the cache ?

    ---

  • Answer:

    Yes, because:

  ---

  ---

  ---

  ---

• Using the (associative) cache --- with memory addresses
  • Suppose the content of an Associatve Cache is:

    ---

  • The CPU now makes a read request for the byte at memory address 17

    Question:

    Is this byte found in the cache ?

    ---

  • Answer:

    The byte at address 17 is stored in block number = 4:          17/4 = 4 (integer division !!) Graphically: The byte is in the cache because:

  ---

  ---

  ---

  ---

• Summary on how to use an associative cache
  • Summary

    CPU makes a read request for the content at some memory location (memory address) We compute the block number using the memory address Then we search for the block number in the cache If the block number is found and the corresponding valid bit = 1, then: The value requested is found in the cache (Otherwise, we need to fetch it from memory)

  ---

  ---

  ---

  ---

• Caveat on using an associative cache
  • Caveat:

    We cannot use a sequential search method to search for the block number in a cache !!!

    Reason:

    Sequential search will check a block number in the cache sequentially (= one after another) A cache can have 16 million slots !!! Checking for 16 million block numbers will take a long time !!! It will certainly take longer than 50 nsec !!! (Which is the time needed to fetch the value from the memory !!!)

    ---

    ---

  • Therefore:

    We need to perform parallel search in a cache !!! (Only hardware can do things in parallel; so the solution is a circuit !!!)

  ---

  ---

  ---

  ---

  ---

  ---

  ---

  ---

• Prelim: how to find the block number
  • Fact:

    Computer addresses are expressed in binary inside the computer (Each bit is carried by a copper wire on the computer mother board)

    ---

    ---

  • The following figure shows:

    that:

    Block number is obtained from a (memory) address by: Taking away the last 2 bits from the memory address

    ---

    ---

  • Therefore:

  ---

  ---

  ---

  ---

• Circuitry to check if one entry in Associative Cache contains a cache hit
  • The following diagram is the logic used to check if an arbitrary entry in an Asscociate cache contains the requested value:

    Depicted logic:

    The block number requested by the CPU is equal to the block number stored in the cache entry And the cache entry must be valid

  ---

  ---

  ---

  ---

• Architecture of an Associative Cache
  • The architecture of an Associative cache is as follows:

    Explanation:

    The signal A will be: 1 if the first entry of the cache contains the requested block number and the entry is valid The signal B will be: 1 if the second entry of the cache contains the requested block number and the entry is valid And so on... Therefore: We can compute the Cache Hit signal by: Or of all of the A, B, ... outputs (Any entry that contains the request block number and the entry is valid will result in a cache hit) To obtain tha cached value in the entry we use a AND filter: An cache entry that does not contain a cache hit: the stored value in the cache entry will be filtered out (= become all 0000000...000 bits) An cache entry that contains a cache hit: the stored value in the cache entry will be the output Therefore: The Or value of all these value: will be equal to the stored value in the cache hit entry because: The only non-zero value of all these inputs is the stored value in the cache hit entry

  ---

  ---

  ---

  ---

• Strength and weakness of the Associative Cache
  • Strength: flexibility

    A slot (entry) in an Associative cache can cache a word from any memory location

    ---

    ---

    Weakness: expensive (in term of circuitry)

    The Associative cache needs to uses 1 compare circuit for each cache entry So an Associative cache with 16M entries will need to use 16 million compare circuits (to perform massively parallel comparison !!!)