- Normal (non-pipelined) instruction execution:
- Fetch the
next
instruction from
memory into the
CPU
- Execute the
instruction completely
- Then:
fetch the
next
instruction from
memory into the
CPU
- And so on
- Fetch the
next
instruction from
memory into the
CPU
- We can
distinguish
a number of
phases/steps
in the execution
of an instruction:
- Fetching of the
instruction
- Fetching of the
operands of an
instruction
- Perform the
operation
(e.g., add, subtract, and so on) on
the operands
- Write the
result back to
memory
Or: Write the result back to a register (inside the CPU)
- Fetching of the
instruction
- Also,
notice that:
- Different parts of the
CPU (or mostly
different)
are used for
each phase of the
instruction execution:
- Fetching of the
instruction
- Use the system bus
- Fetching of the
operands of an
instruction
- Uses register outputs and multiplexors connecting to the ALU
- Perform the
operation
(e.g., add, subtract, and so on) on
the operands
- Uses the computational circuits inside the ALU
- Write the
result back to
memory
- Use the register as input (write)
Or: Write the result back to a register (inside the CPU)
- Uses the system bus (just like fetching the instruction... so you can expect problems)
- Fetching of the
instruction
- Different parts of the
CPU (or mostly
different)
are used for
each phase of the
instruction execution:
- Pipelined CPU:
- The circuits
(that we have studied previously)
of CPU is
compartamentalised into
independent unit
- Each unit
perform the task of
a specific phase/step (see above) in the
instruction execution
- The instruction is passed to the next unit as soon as the execution in the previous unit is completed
Graphically:
- The circuits
(that we have studied previously)
of CPU is
compartamentalised into
independent unit
- I will first show you how
a normal CPU
executes instructions:
- Initial state:
- Fetch the
next instruction:
- Execute the
next instruction through
each stage of the
execution:
- And so on:
- Finally:
- Then,
fetch the
the next instruction:
And do the same...
- Initial state:
- A pipelined execution
is as follows:
- Initially:
- Fetch the
next instruction:
- Execute the
instruction in
stage 1 and
pass on to stage 2
In the mean time, fetch the next instruction into stage 1:
- Execute the
instruction instr-1 in
stage 2 and
pass on to stage 3
Execute the instruction instr-2 in stage 1 and pass on to stage 2
In the mean time, fetch the next instruction into stage 1:
And so on....
- Initially:
- Conclusion:
- The CPU is executing many (different) instructions (in various stages of execution) at the same time !!!
Clearly, this is not an easy task.
A number of simplifications are adopted to make pipelining easier to implement
- Simplications in
(computer) instructions:
- Fixed size instructions
- Each instruction has the same # bits (e.g., 32 bits)
Reason:
- Conformity make thing
easier to
implement
(Imagine a car wash: don't you wish that every car is the same length ???)
- Limited number of
instructions
that access
the memory.
- Most instructions will
use register operands
- Memory access is
very difficult to
handle
(One reason is that the CPU must also fetch the next instruction using the memory !!!)
Only the following instructions will access memory:
- ld: load (read data from memory)
- st: store (write data to memory)
- Most instructions will
use register operands
- Reduced number of
addressing modes
- This is the rsult of the Reduced Instruction Set Computer design philosophy.
RISC machine provide:
- Immediate addressing mode (#n)
- Direct addressing mode (Dn)
- indirect with constant offset (m(An)) on one operand
- indirect with register offset (0(An, Dm)) on one operand
In contrast, the M68000 (CISC) also provides:
- indirect with constant offset (m(An)) on both operands (e.g.: move.l 8(A0), 4(A1))
- index mode (= indirect with a constant and a register as offset) (u(An, Dm))
- Fixed size instructions
- The reduced set of
instructions in RISC can
be categorized as
follows:
- ALU instructions
- These instructions only
used registers/constants as
source/destination operands
Instruction format: OPER Src-Reg1, Src-Reg2, Dest-Reg OPER Src-Rge1, Constant, Dest-Reg - Examples:
ADD R3, R1, R2 // R3 = R1 + R2 SUB R3, R1, #2 // R3 = R1 - 2
- These instructions only
used registers/constants as
source/destination operands
- Memory instructions
- They are: ld and
st
Instruction format: LDR R3, [Reg1 , Reg2] // R3 = memory value at addr(Reg1+Reg2) LDR R3, [Reg1 ,#const] // R3 = memory value at addr(Reg1+const) STR R3, [Reg1 , Reg2] // Store R3 in memory at addr(Reg1+Reg2) STR R3, [Reg1 ,#const] // Store R3 in memory at addr(Reg1+const)Only these instructions used operand in the memory
- Examples:
LDR R3, [R1 , R2] // R3 = value stored in memory address R1+R2 STR R3, [R1 , #2] // Store R3 into memory located R1+2
- They are: ld and
st
- BRANCH instructions
- These instructions
updates the
program counter (PC)
Instruction format: BRA label BEQ label BNE label etc....Note:
- You will see that
the branch instruction will
cause problems for
a pipelined CPU
(The effect of a branch is like driving at highspeed (e.g., 200 mph) and then make a change in direction (= turn).....)
- You will see that
the branch instruction will
cause problems for
a pipelined CPU
- These instructions
updates the
program counter (PC)
- ALU instructions