Review: solving the read-after-write data hazard caused by an ALU instruction

Solution: we add a short-cut to allow the ID stage to fetch the new value(s) ASAP

I will now illustrate the solution using an example

Example on how the data forwarding technique solves the ALU instruction read-after-write hazard

Example program with (multiple) read-after-write data hazard:

I will show you how data forwarding circuitry operates using these instructions

Example on how the data forwarding technique solves the ALU instruction read-after-write hazard

Cycle 1: instruction add r1,r2,r3 fetched into IR(ID):

The ID stage will fetch the operands while the IF stage will fetch the next instruction

Example on how the data forwarding technique solves the ALU instruction read-after-write hazard

Start 2: ID stage fetches operands R2,R3, IF stage fetch add r4,r1,r4

 

Example on how the data forwarding technique solves the ALU instruction read-after-write hazard

End 2: Operands R2,R3 fetched, add r4,r1,r4 fetch

Notice I have shown the instruction codes (with source and destination reg #'s)

Example on how the data forwarding technique solves the ALU instruction read-after-write hazard

Start 3: EX stage adds R2+R3, ID stage fetches operands R4,R1, IF stage fetch add r5,r1,r5

Notice the ID stage fetches an old value from R1 - new R1 value is being computed in EX stage

Example on how the data forwarding technique solves the ALU instruction read-after-write hazard

End 3: R2+R3 stored in ALUo and FW1 !!

Notice the new R1 value in FR1 is available as operand through the MUX !!!

Example on how the data forwarding technique solves the ALU instruction read-after-write hazard

Start 4: MEM: No op , EX: adds R4+R1, ID stage fetch R5,R1, IF stage fetch add r6,..

Notice: MUX detects that srg reg #1 == tag1 and selects FR1 as operand #1 !!!

Example on how the data forwarding technique solves the ALU instruction read-after-write hazard

End 4: EX: computes 240+1, new R1 stored in FW2 and can be used by next instruction !!

Notice the new R1 value in FR2 is available as operand for one more instruction !!!

Example on how the data forwarding technique solves the ALU instruction read-after-write hazard

Start 5: MEM: No op , EX: adds R5+R1, ID stage fetch R6,R1, IF stage fetch add r7,..

Notice: MUX detects that srg reg #1 == tag2 and selects FR2 as operand #1 !!!

Example on how the data forwarding technique solves the ALU instruction read-after-write hazard

End 5: EX: computes 240+2 --- the new R1 is no longer needed (removed from FW regs) !!

Notice the new R1 value no longer in the forwarding registers (because the ID stage can get the new value from the register R1 from now on !!!)

DEMO (using Aaron's pipelined CPU)

  • Execute this command on a lab machine: 

       /home/cs355001/demo/pipeline/4a-ALU-hazard-sol

    Program being executed: 

              10  12    // mov r1,#12
        18  192   // mov r2,#192
        26  48    // mov r3,#48
        34  1     // mov r4,#1
        42  2     // mov r5,#2
        50  3     // mov r6,#3
        58  4     // mov r7,#4
        0   0     // nop
        0   0     // nop
        0   0     // nop
        0   0     // nop
        8   19    // add r1,r2,r3  (R1=R2+R3)
        32  33    // add r4,r1,r4  (R4 = R1 + R4) (R1 forwarded)
        40  41    // add r5,r1,r5  (R5 = R1 + R5) (R1 forwarded)
        48  49    // add r6,r1,r6  (R6 = R1 + R6)
        56  57    // add r7,r1,r7  (R7 = R1 + R7)