Review: instruction encoding of the ldr instruction

The LOAD instruction encoding format (meaning of the bits in the instruction):

I will only discuss the register as 2nd source operand (the constant operand is similar)

How the pipeline CPU executes ldr r1, [r2,r3]

Clock cycle 1: The IF stage fetches the instruction into the IR(ID) register

I have include the instruction code in binary

How the pipeline CPU executes ldr r1, [r2,r3]

Start of clock cycle 2: the ID stage fetch all possible source operands

How the pipeline CPU executes ldr r1, [r2,r3]

End of clock cycle 2: all source operands are fetched - but only R2 and R3 will be used

Notice: the instruction is moved into the IR(EX) register

How the pipeline CPU executes ldr r1, [r2,r3]

Start of clock cycle 3: the EX stage operates on the correct source operands

The EX stage computes the memory address R2+R3 used by ldr r1,[r2,r3] !!!

How the pipeline CPU executes ldr r1, [r2,r3]

End of clock cycle 3: the result is stored in ALU Output and the Data Mem Addr registers

Notice: the instruction is moved into the IR(MEM) register

How the pipeline CPU executes ldr r1, [r2,r3]

Start of clock cycle 4: the MEM stage executes the ldr r1, [r2,r3]

The MEM stage sends a READ request and the address R2+R3 on the system bus. WAIT !!!

How the pipeline CPU executes ldr r1, [r2,r3]

Start of clock cycle 4: notice that the IF stage also wants to use the system bus

The MEM stage has priority over the IF stage !!! The IF stage must be stopped (paused) !

How the pipeline CPU executes ldr r1, [r2,r3]

Solution: when MEM stage detects a ldr instruction, it sends a STALL signal to the IF stage

The STALL signla will (1) disable the clock signal in the IF stage (2) send a NOP instr to IR(ID)

How the pipeline CPU executes ldr r1, [r2,r3]

The MEM stage executes the ldr instruction and sends a READ request on the system bus:

In response, the memory sends back the data requested on the data bus

How the pipeline CPU executes ldr r1, [r2,r3]

End of clock cycle 4: the memory data (1234) is stored in the Load Mem data register

Notice: a harmless NOP (no-op or "do nothing") instruction is inserted into the IR(ID) register

How the pipeline CPU executes ldr r1, [r2,r3]

Start 5: the ldr instr causes the WB stage to select LMDR as input and update the register R1

How the pipeline CPU executes ldr r1, [r2,r3]

End of clock cycle 5: the result 1234 is stored in the register R1

Notice: the instruction has been into the discarded !! (no longer needed !!!)

DEMO (using Aaron's pipelined CPU)

Execute this command on a lab machine:

/home/cs355001/demo/pipeline/2-ld-instr

Program being executed:

10 65 // mov r1, #65 18 10 // mov r2, #10 26 22 // mov r3, #22 34 1 // mov r4, #1 42 8 // mov r5, #8 58 2 // mov r7, #2 0 0 // nop 0 0 // nop 0 0 // nop 0 0 // nop 0 0 // nop 72 19 // ldr r1,[r2+r3] ( R1=memorylocation[R2+R3] ) 0 1 0 1 // Used to show "NOP insertion" by IF stage 0 1 // NOP instr = 00000000 00000000 0 1 .... 32: 255 254 (11111111 11111110) <--- data loaded into R1)