CS355 Sylabus

Addressing IO devices

As you have seen in the introduction to IO devices, every IO device is controlled by writing some command code into the command register that is attached to the system bus.
The status (idle, busy) of the IO device can be obtained by reading its status register.
So operating an IO device is essentially very similar to reading and writing memory, except that write operations to the command register will make the IO device do a certain operation.
Just like memory, IO devices need to be assigned a unique ID or address
As you know, memory locations also have addresses.
So how can you tell the difference between an address for an IO device and an address for a memory location ?
There are 2 techniques to allow IO devices to be addressed:
- Standard IO
- Memory-mapped IO
Currently, only the Intel Pentium CPU processor uses standard IO, all other CPUs (SPARC, PowerPC, Alpha, etc), uses memory-mapped IO.
In the standard IO technique, IO devices and memory location have separate address spaces
Two "spaces" are separate if there is an external (explicit) signal that identify the space.
For example, there are many "lotto" games in the US. If you have a Big Game ticket with the numbers 1, 2, 3, 4, 5, 6, and the Lotto South draws the 6 winning numbers 1, 2, 3, 4, 5, 6, then although your Big Game ticket has the winning numebrs, you are not a winner.
Similarly, when the CPU signals an address 1234 on the address bus, in standard IO, that address can be used to address a memory location or an IO device.
The CPU has an extra explicit signal that indicates whether the address is a memory location or an IO device:
- The MREQ signal is used to signal memory requests
- The IOREQ signal is used to signal IO requests
When the CPU wants to access (read/write) a memory location, it asserts the MREQ signal (and simultaneously do not assert IOREQ).
Similarly, when the CPU wants to access (read/write) an IO device, it asserts the IOREQ signal (and simultaneously do not assert MREQ).

The assembler programmer (who programs the CPU) must therefore have 2 different types of assembler instructions to his/her disposal that allow him/her to assert the MREQ or IOREQ signals.

In the Intel processor (which is the only processor that uses standard IO), the programmer uses:

MOV assembler instruction to access the memory - hence, when the CPU executes a load or store instruction, it will assert the MREQ signal.
IN (input) and OUT (output) assembler instruction to access IO devices - hence, when the CPU executes a input or output instruction, it will assert the IOREQ signal.

Here is an Intel assembler code manual for your perusal: click here

The MOV instruction is described in section 30.3
The IN/OUT instructions are described in section 30.11

In the memory-mapped IO technique, IO devices and the main memory share the same address space
In memory mapped IO, the manufacturer of the computer system must partition the address space (the range of address values) into:
The 2 sets of addresses must be disjoint (no overlap) !!!

Example partition:

Address (binary) Use for ----------------------------------------------------------- 00000000 00000000 00000000 00000000 Memory 00000000 00000000 00000000 00000001 Memory 00000000 00000000 00000000 00000011 Memory .... 11100000 00000000 00000000 00000000 Memory 11100000 00000000 00000000 00000000 Memory .... 11101111 11111111 11111111 11111111 Memory 11110000 00000000 00000000 00000000 IO device 11110000 00000000 00000000 00000001 IO device .... 11111111 11111111 11111111 11111111 IO device

If the last 4 bits of the address = 1111, then the CPU wants to address an IO device. Otherwise, the CPU wants to addres the memory

After determining the two (disjoint) sets, the manufacturer will construct selection circuitries that implement the partition.

In the above example, we can use the following circuit to determine whether the CPU wants to address the memory or an I/O device:

In other words:

there is no extra explicit signal to indicate whether an address is for a memory location or an IO device.
The value of an address will determine whether the main memory or an I/O device is addressed

Therefore, when the CPU sends out an address, there is no way to tell by only looking at all the signals from the CPU if the address was for a memory location or for an IO device. (But ofcourse there must be a way to tell the difference, just not by looking at the signal from the CPU).

In general, memory-mapped IO is constructed as follows:

The MREQ signal is used to signal both memory and IO device requests
When the CPU wants to access (read/write) a memory location or an IO device, it always asserts the MREQ signal.

The select circuitries (in magenta, cyan and light blue) in the above figure determines which address values will activate the memory and a particular IO device.
Clearly, unlike in standard IO, there is no need to have 2 different types of assembler instructions (one type for accessing memory and the other for accesing IO device).
For example, the M68000 uses memory mapped IO and it can use the move instruction to access the memory and IO device.
(For those students that plan to take Operating Systems - you will see that the addresses 1400 - 15FF (Hex) are reserved for IO devices in emacsim)
For example, a simple partition scheme is to have addresses that starts with 0 to denote a memory location and address that start with 1 to denote an IO device.
Then we can use the remaining 31 bits of the address as the actual address portion for selecting a memory location or IO device.
The wiring scheme for the above partitioning of the address space is given in the following diagram:
- Notice that the left most bit of the address is used along with MREQ to determine if the memory or an IO device will be enabled.
You may wonder which addressing scheme is better:
- Standard I/O
- Memory-mapped I/O
Well, there is no clear advantage for either scheme, it's a matter of taste, very much like the big endian/little endian choice.
Perhaps this phenomenon is related to the big endian/little endian phenomenon, because only the Intel CPUs uses both little endian encoding and standard IO. The rest of the world uses big endian and memory-mapped IO.