CS355 Sylabus

Synchronous Buses

As we saw in the last webpage:
- Bus protocols contains a rigid set of steps that communicating devices must perform to complete a data transfer operation (buses are always use to perform data transfer)
- These steps are pre-planned, i.e., specified a priori.
  (You can find analogies of bus protocols in archaic practices like a visit from a foreign head of state. The protocol dictates that the foreign head of state must be received in a certain manner. One of the steps in the reception is the "inspection of the guards").
A bus is called "synchronous" if the steps of the bus protocol is guided by a clock signal
The clock signal that guides the bus protocol is called the "bus clock".
(Do not confuse this clock with the 4-phase clock inside the CPU, these are 2 different clocks and they have nothing to do with each other. There are many clocks inside a computer, each one clock signal paces its own little subsystem within the computer).
The steps in an synchronous bus protocol are pre-planned using the bus clock.
Let's consider the mundane task of "frying an egg".
The steps to successfully fry an egg consist of:
1. Turning on the stove
2. Putting a pan on the stove
3. Poor oil in the pan
4. Break the egg and put it in the pan
5. Wait until the egg is cooked
6. Remove the egg and turn off the stove
7. (As any examplary student would do it, we ignore the dish washing step... :-))
To fry an egg successfully, the steps must be followed in a specific order, e.g., you cannot put the egg in, fry it and then poor the oil (yes, human knows that, but try telling that to a computer... you have to spell it out to machines... it's worst than teaching kindergarten kids...)
Some steps can be do simultaneously but the design will be more complex (need more hardware), so sometimes, even when steps can be performed simultaneously, the bus protocol designer may opt to make the step happen sequentially.

In a synchronouse protocol, the steps of the protocol are planned to occur at the moments that the clock signal changes in value (device can only detect changes in the clock)

The start of a synchronous protocol is always at a rise of the bus clock signal.
The last event in a synchronous protocol is usually planned to occur at a fall of the bus clock signal (so that the next protocol can start at a rising edge).

Here is an example of a planning of the "fry an egg" steps using a clock:
- At rise of clock: Turning on the stove and putting a pan on the stove
- At fall of clock: Poor oil in the pan
- At rise of clock: Break the egg and put it in the pan
- At fall of clock: If eyes signals that the egg is ready, remove the egg and turn off the stove
Here is an example of a completion of the synchronous egg frying protocol:
Note that when the protocol finishes, we can start a new protocol immediately if we wanted to - if you build this protocol with a finite state automata, you will get a lean and mean egg-frying machine :-)
The same principle applies when devices inside a computer communicate with each other:
- A number of things must happen
- and the things must happen in a particular order
- The steps are preplanned with a clock signal
The (rigid) steps that must happen in a data transfer depends on the type of operation performed.
- In a read operation where the CPU reads from memory:
  1. CPU sends out address value, asserts MREQ and READ
    (asserting MREQ signals that a request is made to memory, asserting READ signals that it is a read operation and the address value will provide the memory the necessary information to retrieve the data.)
  2. CPU waits until the memory is sending out the data on the data bus
  3. CPU copies the data into the MBR
  4. CPU remove the address and the memory read request
    (NOTE: unlike our student, the CPU has to clean up his mess....)
- In a write operation where the CPU updates the memory:
  1. CPU sends out the address and data values, asserts MREQ and WRITE (= not asserting READ)
    (asserting MREQ signals that a request is made to memory, asserting READ signals that it is a read operation and the address and data value will provide the memory the necessary information to update the right location with the right data.)
  2. CPU waits until the memory has finish writing
  3. CPU remove the address, data values and the memory write request
    (again, unlike our student, the CPU has to clean up his mess....)
- Here is a planning of the steps of in a synchronous read protocol using a clock:
  - At rise of clock: send out address value
  - At fall of clock: assert MREQ and READ
  - At fall of next clock: If memory signals that the data is ready, copy data into MBR and clean up (remove address value, MREQ and READ) If memory signals not ready (asserts WAIT), the CPU will try again at the next falling edge of the clock.
  The events schedule depicted schematically with a clock:
  
  Here is an example of a completion of the synchronous read protocol:
- Notice that:
  - The READ and MREQ signals are asserted when their values are low (i.e., ZERO), so the CPU is signalling a read operation when READ and MREQ are ZERO.
  - Although an action is plan to occur at the rise/fall of the bus clock, there is (always) some delay between the rise/fall of the clock (that is used to plan an event) and the occurence of the event - it's simply physics: the output of the bus clock (electricity) needs some time to travel from the bus clock (quartz) to the CPU. In the figure, the delay times are:
    - T_AD: time between detecting the rise of bus clock and sending out the address value
    - T_MD: time between detecting the fall of bus clock and asserting out the MREQ signal
    - T_RD: time between detecting the fall of bus clock and asserting out the READ signal
  - In the read protocol, the memory must send the data out first and then tell the CPU that the data is ready. If the memory does these steps in reverse (tell the CPU that the data is ready and then send the data out), there will be a chance that the CPU may copy wrong values.
  - Also, the CPU must copy the data on the databus into the MBR first and then remove the address value, the MREQ and READ (which signals to the memory that the data is no longer needed). If the CPU does these steps in reverse (tell the memory that the data is no longer needed and then copies the data into MBR), there will again be a chance that the CPU may copy wrong values.
- Advantage:
- Disadvantage: