CS355 Sylabus

Asynchronous Buses

A bus is called "asynchronous" if the steps of the bus protocol is NOT guided by a clock signal
Recall that the purpose of a bus protocol is to enable two brainless devices to communicate with one another by spelling out every step of the process.
The bus protocol makes sure that devices know each others' state of affair when they take the next step.
In an asynchronous protocol, the communicating devices signal each other using special control signals.
A simple asynchronous communication protocol can be constructed by using two control signals:
- MSYNC: Master Sync signal
  - Signals that the "master" device is ready (ready for what will depend on the steps of the communication protocol)
- SSYNC: Slave Sync signal
  - Signals that the "slave" device is ready (again, ready for what will depend on the steps of the communication protocol)
In data communication, the device that initiates the communication is called the Master Device
The device that the master device wants to communicate with is called the Slave Device
In a read operation (where the CPU requests that the memory sends it some data), the CPU is the master device and the memory is the slave device.
Let's look at the steps of the read protocol again where the CPU reads memory data:
1. CPU sends out address value, asserts MREQ and READ
  (asserting MREQ signals that a request is made to memory, asserting READ signals that it is a read operation and the address value will provide the memory the necessary information to retrieve the data.)
2. CPU waits for the memory to signal that it (= memory) is ready (ready means: data is ready)
3. CPU copies the data into the MBR when memory is ready.
4. CPU remove the address and the memory read request

Here are a planning of the steps of in an asynchronous read protocol where we use MSYNC and SSYNC to allow the CPU and memory signal to each other that they are "ready":

CPU (master) sends out address value, asserts MREQ and READ
(asserting MREQ signals that a request is made to memory, asserting READ signals that it is a read operation and the address value will provide the memory the necessary information to retrieve the data.)
CPU (master) asserts MSYNC [I am ready (done), it's your turn...]
NOTE: CPU must assert MSYNC only after it has sent out the address, asserted MREQ and READ (because with MSYNC asserted, the address values, MREQ and READ must be correct - MSYNC asserted means ready).
CPU (master) waits for the memory (slave) to signal that it (= memory) is ready (ready means: data is ready)
CPU copies the data into the MBR when SSYNC is asserted.
CPU remove MSYNC
CPU remove the address and the memory read request
NOTE: CPU must drop the address, MREQ and READ only after it has dropped MSYNC (because with MSYNC asserted, the address values, MREQ and READ must be correct).

Here is an example of a completion of the asynchronous read protocol:

The protocol depicts the following sequence of events:

Initially, no valid signals are sent on the system bus:
Some times later, the CPU sends out valid signals for address, MREQ and READ:
Afterwards, the CPU sends out MSYNC - signalling that all neccesary information are now ready:
Some more time later, the memory sends out the requested data on the data bus:
Only then, the memory sends out SSYNC - signalling that data on the databus are now ready:
The CPU is now allowed to read the data !!!
AFter the CPU finish reading the data, it remove the MSYNC signal -- telling the memory not to use the address, MREQ and R/W signals:
Then the CPU remove the address, MREQ and R/W signals:
When the MREQ signal is removed, the memory will emove the SSYNC signal first (so no device are allowed to read the memory data):
And then the memory removes the data from the databus:
Now we are back to the initial state and another bus cycle can start !!!

Notice that:
- The data on the databus is guaranteed to be correct when MSYNC and SSYNC are asserted:
- So if you make the CPU perform the read during this period, you will guarantee that it reads the correct value.
- The asynchronous bus protocol also spells out the steps rigidly that will lead to this state (and also specify steps to return the system back to its original state).
A real timing diagram:
- Here is the timing diagram for M68000:
  This diagram contains timing for 3 different operations: read, write and a read operation to a slow memory device so that the M68000 CPU has to wait (see the w above)