Background information

A CPU is an electronic machine that process information in stages
Schematically:

Background information

The data is first processed by stage 1:
Example: stage 1 selects the correct source registers

Background information

The processed data is then processed by stage 2:
Example: stage 2 selects the add operation on source registers

Background information

Desired behavior:
Graphically:

DEMO: /home/cs355001/demo/circuits/shift-register

A simple experiment using D-latches

The following simple circuit shows a problem with D-latches when we try to build a independent staged computation device with them:

In this circuit, each of the D-latch (= 1-bit-memory circuit) will copy the bit stored in the prior 1-bit-memory circuit into itself.

DEMO the behavior: /home/cs355001/demo/circuits/shift-reg-D-latch

A simple experiment using D-latches

What does a indepedent staged processing behavior look like ?
DEMO the staged processing behavior:
/home/cs355001/demo/circuits/shift-register
Observed behavior with D-latches:

We will first study circuit timing and then build a accurate 1-bit-memory circuit

Background information

Clock signal:

Every circuit component inside a computer is control by a block electric wave form that look like this:
This signal that paces the operations performed by the computer is called a clock signal

The clock signal or a signal derived from the clock signal will be connected to the clock inputs of each memory components (e.g.: D-latch) in the computer.

Active period of a memory circuit

A memory circuit (such as a D-latch) is active when:
Q: what are the active periods in the clock signal for the D-latch circuit ?

Active periods for the D-latch circuit

The periods in a clock signal when a D-latch is active are when clock signal = 1: (DEMO: d-latch)

Inactive periods for the D-latch circuit

When write (clock) signal = 0, the input signals of the SR-latch are:
which cause the output to remain unchanged

Latches: level active (level triggered) memory devices

The D-latch that we have constructed:

is active when the clock level = 1:

Latches: level active (level triggered) memory devices

There is also another version of D-latch:

that is active when the clock level = 0:
Note: we will not use this version of D-latch in CS355

Latches: level active (level triggered) memory devices

Latches are memory devices that are active when the level of the write (clock) signal is leveled (i.e.: clock=0 or clock=1)
Latches are (therefore) level active (level triggered) memory devices
The active period of latches are considered very long (when compared to time period of a rising/falling edge of the clock)
We will study a memory circuit that have very short active periods:
These are edge active (edge triggered) memory circuits
(They are called flip flops)

The D-flip flop circuit

Consider the following circuit (it's called a D-flip flop):

What are the active periods of this circuit ?

Use the DEMO to find out: /home/cs355001/demo/circuits/d-flipflop-demo

The D-flip flop circuit

Let's eliminate the non-active periods:

The D-flip flop is not active during clock level = 0:

The D-flip flop circuit

Let's eliminate the non-active periods:

The D-flip flop is not active during clock level = 1:

The D-flip flop circuit

Notice that we can (= are able to) update the output = input (see demo):

So the D-flip flop must have an active period that is edged:

Flip flops: edge active (edge triggered) memory devices

Flip flops are memory devices that are active when the clock signal changes from 0 → 1 (rising edge) or from 1 → 0 (faling edge)
Flip flops are (therefore) edge active (edge triggered) memory devices
The active period of flip flops are extremely short (nano seconds !)
The staged processing behavior can be achieved using D-flip flops !!!

DEMO: /home/cs355001/demo/circuits/shift-register

Accurate and inaccurate memory circuits

Flip flops are accurate memory circuits:
During this very short active period, the input value can not change
The value captured is very precise and unambiguous
Latches are slow memory circuits:
During this long interval of active period, the input value could have changed
To ensure correct operation:
The input signal must remain unchanged for the entire duration of the active period

Fast and slow memory analogy: shutter speed of a camera

In photography, using a faster shutter speed will capture a more accurate scene/state:

Because a shorter exposure time does not allow much motion...

Introducing EDiSim's built-in D-flipflop component

EDiSim has a built-in D-flipflop component.
Syntax:
Note: the output value is initially set to UNKNOWN !!
In addition to the usual inputs: input and clock, the Dff component has 2 extra inputs:
When set=0 and reset=0, the Dff component will operate normally D-flipflop (as described in the lecture material)

Introducing EDiSim's built-in D-flipflop component - Examples

The D-flipflop components will initially have an UNKNOWN value for output:

The ORANGE color in the probe means: UNKNOWN value
DEMO: /home/cs355001/demo/circuits/sample-Dff

Introducing EDiSim's built-in D-flipflop component - Examples

You can initial the output = 0 with reset=1 (and set=0):

The LIGHT GREEN color in the probe means: value=0

Introducing EDiSim's built-in D-flipflop component - Examples

You can initial the output = 1 with set=1 (and reset=0):

The DARKER GREEN color in the probe means: value=1

Introducing EDiSim's built-in D-flipflop component - Examples

When set=0 and reset=0, the Dff component will operate as a D-flipflip:

The input value will be written to the output using the clock signal