The array signal notation in EDiSim

  • From now on, you will often use binary numbers as input/output like this: 

       a7 a6 a5 a4 a3 a2 a1 a0 // = an 8 bits binary number

    (We always put the most significant (binary) digit at the left (e.g.: 10001001)

  • There is a shorter array notation available in EDiSim syntax: 

       a[7..0] or a[7-0] ≡ a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0]

    The signal names defined by a[7..0] (or: a[7-0]) are a[7], a[6], ..., a[0]

  • Important note:

      • a[0] and a0 are different signal names !!

Example using the array signal notation
 

Previously, you saw the 4-bit-adder circuit in EDiSim code using non-array signal notation: 

Define FourBit_Adder   a3 a2 a1 a0 b3 b2 b1 b0 | CarryOut s3 s2 s1 s0;
   Full_Adder ch ZERO  a0 b0  | c1       s0;
   Full_Adder cf c1    a1 b1  | c2       s1;
   Full_Adder cd c2    a2 b2  | c3       s2;
   Full_Adder cb c3    a3 b3  | CarryOut s3;
Endef;

It is rather cumbersome to write a long series of digits

Example using the array signal notation
 

Using the array signal notation of EDiSim, the same circuit can be re-written as: 

Define FourBit_Adder   a[3..0] b[3..0] | CarryOut s[3..0];
   Full_Adder ch ZERO  a[0] b[0]  | c1       s[0];
   Full_Adder cf c1    a[1] b[1]  | c2       s[1];
   Full_Adder cd c2    a[2] b[2]  | c3       s[2];
   Full_Adder cb c3    a[3] b[3]  | CarryOut s[3];
Endef;

Note that we must change a0 ⇒ a[0], a1 ⇒ a[1], ... b0 ⇒ b[0], b1 ⇒ b[1],... s0 ⇒ s[0], s1 ⇒ s[1],... inside the body of the definition !!!

(Because:   a0 ≠ a[0], a1 ≠ a[1], ... b0 ≠ b[0], b1 ≠ b[1],... s0 ≠ s[0], s1 ≠ s[1],... !!!)

DEMO: /home/cs355001/demo/circuits/4-bit-adder.arr