0. Project Preparation

• Make a assignment sub-directory and copy the prepared files:

  mkdir ~/cs355/hw4 cp /home/cs355001/Handouts/hw4/* ~/cs355/hw4

  You will copy these files:

  basic.h - the commonly used circuit components in the CS355 assignments Full_Adder aa c_in a b | c_out sum; You can use the Full_Adder component in assignment hw4 to make the PC component help-CLK - the main simulation program file to test the CLK circuit It creates switches and probes to help you test the CLK circuit (macro) that you must make in this assignment help-PC - the main simulation program file to test the PC (Program Counter) circuit It creates switches and probes to help you test the PC circuit (macro) that you must make in this assignment clock.h - Skeletal assignment file - contains the circuits (macro definitions) that you must make for this assignment (turn in THIS file !) sample-mux - Sample EDiSim program to show you how to use the Mux built-in circuit sample-Dff - Sample EDiSim program to show you how to use the Dff built-in circuit

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• You will need to learn to use the Mux (multiplexor) built-in component to do this assignment:

  EDiSim doc page: click here Syntax: Mux coord N-controls | 2^N inputs | 1 output ; Inputs and outputs can be arrays of signals !!! Examples: Mux aa sel | B A | out; // Mux has 1 select signal, so you need to use 2 inputs (and 1 output) // If sel = 0 then out = A // If sel = 1 then out = B Mux aa sel[1..0] | D C B A | out; // Mux has 2 select signals, so you need to use 4 inputs (and 1 output) // If sel[1] = 0 and sel[0] = 0 then out = A // If sel[1] = 0 and sel[0] = 1 then out = B // If sel[1] = 1 and sel[0] = 0 then out = C // If sel[1] = 1 and sel[0] = 1 then out = D Mux aa sel[1..0] | D[3..0] C[3..0] B[3..0] A[3..0] | out[3..0]; // You can use arrays (e.g.: A[3..0]) as inputs and outputs of the Mux // If sel[1] = 0 and sel[0] = 0 then out[3..0] = A[3..0] // I.e.: out[3] = A[3], out[2] = A[2], out[1] = A[1] and out[0] = A[0] // If sel[1] = 0 and sel[0] = 1 then out[3..0] = B[3..0] // If sel[1] = 1 and sel[0] = 0 then out[3..0] = C[3..0] // If sel[1] = 1 and sel[0] = 1 then out[3..0] = D[3..0] // The ability to switch an array of signals will help when // you connect the registers to the ALU later in assignment 6 Try: /home/cs355001/bin/cs355sim sample-mux to see the operation of the built-in Mux circuit

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• You will need to learn to use the Dff (D-flipflop) built-in component to do this assignment:

  EDiSim doc page: click here Syntax: Dff coord set input clk reset output ; If set = ONE and reset = ZERO, then output = ONE ("set") If set = ZERO and reset = ONE, then output = ZERO ("reset") If set = ZERO and reset = ZERO, then output = input when the clk signal is clicked twice (set = ONE and reset = ONE is not used) Examples: Dff bb-cb ZERO inp Clk Reset out ; // If we only want the Reset function Try: /home/cs355001/bin/cs355sim sample-Dff to see the operation of the built-in Dff circuit

1. Project overview

In this assignment, you will design and implement another two components for your computer, which are:

a 4-phase clock               a Program Counter (PC)

Both circuits are implements as macros, so you will be writing two macros for this assignment.

You can find more information on writing user defined components as macros here: click here .

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Just like in assignment hw3, I have provides you with 2 circuit test environment files and skeleton assignment program file.

Write the circuits inside the skeleton assignment program file

The circuit test environment program files are used to test your assignment

2. Project Assignment

• Part 1: Write a macro called Four_Phase_Clock that defines the 4-phase clock that was (or soon to be) discussed in class (see more detail here: click here)

  Background: the CPU's job is to execute an instruction. In order to execute an instruction correctly, a number of events must happen in a specific chronological order. The events are always "change the value of some (special/general purpose) registera". Since registers are updated with a clock signal, the chronological ordering of the (register ipdate) events can be control using a series of clock signals that where each clock signal is "displaced" (see figure below). In the first part of the assignment we will use a 4 state FSM (finate state machine) and a decoder to create a 4 phase clock.

  Description of the input and output signals of the 4 phase clock circuit:

  The 4-phase clock circuit component (= macro) has 2 inputs and 4 outputs: The inputs are: Reset: used to reset the 4 phase clock to phase 1 Clk: signal used to make the 4 phase clock move to the next phase The outputs of the 4 phase clock are: Ph1: phase 1 signal of the 4 phase clock Ph2: phase 2 signal of the 4 phase clock Ph3: phase 3 signal of the 4 phase clock Ph4: phase 4 signal of the 4 phase clock

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  The macro header of the 4 phase clock is as follows (given in the prepared file):

  Define Four_Phase_Clock Reset Clk | Ph1 Ph2 Ph3 Ph4; /* Write the 4-phase clock circuit here */ Endef;

  The Four_Phase_Clock cuicuit will be implemented using a FSM (Finite State Machine)

  The meaning of inputs are as follows:

  Reset: When Reset = ONE, it will reset the FSM in 4-phase clock to the state 00 which corresponds to the phase 1 of the 4 phase clock When Reset = ZERO, the FSM in the 4-phase clock will transit to the next state each time you turn the Clk signal OFF and then ON The state transition diagram is given below. Clk = used to make the FSM in the 4-phase clock move to the next state (will only work when Reset = ZERO)

  In addition to making the FSM, you need to use the state of the FSM to control 4 output signals. The output signals of the 4 phase clock are controlled by the state of the FSM as follows:

  Ph1: equals to 1 if the FSM in the 4 phase clock is in state 00, otherwise equals to 0 Ph2: equals to 1 if the FSM in the 4 phase clock is in state 01, otherwise equals to 0 Ph3: equals to 1 if the FSM in the 4 phase clock is in state 10, otherwise equals to 0 Ph4: equals to 1 if the FSM in the 4 phase clock is in state 11, otherwise equals to 0

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  How to make the 4-phase clock component

  To implement the 4-phase clock, you will first implement a 4-states Finite State Machine with the following state transitions:

  The Finite State Machine will have no input signal !!! (That means the transitions of FSM will always be the same - in our case, it goes in circles...).

  The circuit does have 2 input switches that perform the following functions on the D-flipflops of the FSM:

  A switch (the Reset input signal connected to key 1) used to reset the FSM: When the Reset signal is equal to ONE, it forces both Dffs of the 4-phase clock to ZERO. When the Reset signal is equal to ZERO, the Dffs will operate as ordinary Dffs (see: click here) A switch (the Clk input signal connected to key 0) that functions as the manual clock that advances the state of the FSM.

  You must first implement the Finite State Machine (FSM) given in the above figure.

  After you finish the FSM, add additional combinatorial circuit (figure out what you need yourself) to translate the state of the FSM to the 4 outputs Ph1, Ph2, Ph3 and Ph4 of the clock:

  Ph1 will only be 1 if and only if the Finite State Machine is in state 00 Ph2 will only be 1 if and only if the Finite State Machine is in state 01 Ph3 will only be 1 if and only if the Finite State Machine is in state 10 Ph4 will only be 1 if and only if the Finite State Machine is in state 11

  If we plot the outputs of the 4 signals of the 4-phase clock over time, it will looks as follows: (time flows from left to right in the figure below, so the signal further to the right is "later" in time)

  The state change of the 4-phase clock is controlled by the manual clock input signal (associated to key 0)

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  Testing the 4-phase clock component

  After you have written the CLK macro in the file clock.h, you can test the CLK circuit using this command:

  /home/cs355001/bin/cs355sim help-CLK

  The test circuit (help-CLK) that you see will look as follows:

  You can interact with the help-ALU test circuit as follows: Press a to reset the 4-phase clock (Press a again to allow the 4-phase clock to run)              Press 0 to run the 4-phase clock

  Details on how to test the 4-phase-clock macro is given next.

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  How to verify the correctness of your CLK circuit: (what is the correct behavior)

  When the simulation starts, you will see the following state: Press a: you will see the clock go to phase 1 immediately: Press a again --- you need to release the reset: The clock circuit can now run. If you press 0 repeatedly and you will see: For every 2 presses, the 4 phase clock will advance 1 phase. You will see the light move to the right and then wrap around at the end (i.e.: first light will light up after it wraps around) You can observe the correct behavior by running this program and use the above instructions to interact with the circuit: /home/cs355001/Solutions/hw4-CLK

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• Part 2: Write a macro called PC_with_Branching that implements a Program Counter (PC) circuit with a branch function.
  Background information: in CS255, we learned that the CPU can perform 2 kinds of program flows: in order (next instruction follows current instruction) and out of order (next instruction is store elsewhere). The PC_with_Branching circuit will show you how these 2 kinds of program flows are implemented in hardware. When the Branch is ZERO, the CPU will perform in order program flow (PC is incremented by 1) and otherwise, the CPU will branch to an (input) address given by PC[7..0]

  The macro header is as follows:

  Define PC_with_Branching Reset Clk Branch Addr[7..0] | PC[7..0]; /* Write your PC_with_Branching component here */ Endef;

  The inputs of the PC_with_Branching component are as follows:

  Reset: When Reset = ONE, it will reset the Program Counter to 00000000 When Reset = ZERO, the PC component will be updated to the next PC value each time you toggle the Clk signal OFF and then ON The PC value is equal to PC+1 when Branch=0 The PC value is equal to the Addr input when Branch=1 Clk = make the Program Counter take on the next program address value The next program address value of the PC depends on the branch signal !!! Branch: the branch indication signal Effect: If Branch = 0, then the next program address value taken on by the PC is equal to current PC value + 1 If Branch = 1, then the next program address value taken on by the PC is equal to the Address input value Addr[7..0] Addr[7..0] = the 8 bits branch address The PC_with_Branching circuit will taken on the value Addr[7..0] when Branch = 1 (and you give a Clk signal to the PC_with_Branching circuit)

  The output signals of the PC_with_Branching component are as follows:

  PC[7..0] = 8 bits value representing the address stored in the PC component

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  How to make the PC_with_Branching circuit

  The PC_with_Branching circuit was not discussed in class (will be discussed later) and but I will show you how to make it.

  Schematically, the PC_with_Branching circuit looks like this:

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  The input parameters of the PC_with_Branching component have the following functions:

  Reset: is used to reset the 8 Dffs of the PC to the value 0 Branch: controls a multiplexor to select the input of the 8 Dffs used to store the value of the PC If Branch=0, the multiplexor will select the PC+1 input. If Branch=1, the multiplexor will select the (Branch) Address input. Important note: use the EDiSim built-in multiplexor ! (because just one built-in multiplexor can multiplex all the 8 bits in the PC !!!) Clk: is the clock signal of the 8 Dffs used to store the value of the PC

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  Testing the PC_with_Branching circuit

  After you have written the PC_with_Branching macro in the file clock.h, you can test the PC_with_Branching circuit using this command:

  /home/cs355001/bin/cs355sim help-PC

  The test circuit (help-PC) will look as follows:

  You can interact with the help-ALU test circuit as follows: Press a to reset the PC component Use key 1 to select branch/no branch: Branch signal = 0 means: don't branch (i.e.: continue to next instruction) Then PC will increase its address after each clock signal Branch signal = 1 means: branch to the given address Then PC value will change the address value after a clock signal Use the keys 2, 3, 4, 5, 6, 7, 8, 9 to set the 8 bit (branch) address Key 0 is the clock signal for the PC component

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• How to verify the correctness of your PC circuit:

  When you run /home/cs355001/bin/cs355sim help-PC, you will see this initial state: Press a (= Reset) and you will see the output PC[7-0] go to 00000000 immediately Press a again --- to release the reset so that the PC circuit run normally. While switch '1' (Branch) = 0, when you press 0 repeatedly, you will see that: For every 2 presses, the PC circuit will increase by 1. (I.e.: if you don't branch, the next instruction is found in the memory location that follows the current memory address) This simulate the fact that the CPU will fetch the next instruction located at the next memory address To make the PC branch to a memory address: Set the branch address using the key 2, 3, 4, 5, 6, 7, 8, 9 Press 1 to set Branch = 1 Then press 0 twice The PC output will be equal to the branch address You can observe the correct behavior by running this program and use the above instructions to interact with the circuit: /home/cs355001/Solutions/hw4-PC

5. Turn in

Turn in your "clock.h" file that contains the Four_Phase_Clock and the PC_with_Branching components as assignment hw4 with the following command:

/home/cs355001/turnin clock.h hw4

6. Extension requests

• Each assignment must be turned in before the specified dead line (see class webpage for the deadline)

• You can request upto 3 extensions in the semester without any penalties without any questions asked

  (A 4th extension request will be automatically denied --- personal emergencies and illiness with documentation will receive a "free" extension)

• To request an extenion for this assignment, us the following command:

  /home/cs355001/req-ext hw4

Students will be graded partially on the basis of their programming assignments. These programming assignments are to be treated as examinations, and are expected to be your individual work. While discussions with other students in the course may be permitted or encouraged by your instructor, you should write your program yourself. The mathlab representatives are available to explain error messages, discuss briefly technical details with which you may not be familiar, and give short suggestions as to how you might detect logic errors. The reps should not, however be asked to write part or all of your program. Your instructor (and any teaching assistants assigned to the course) will be glad to help you to the extent that he or she feels reasonable.

Submissions based on other students solutions in prior offerings of the course specifically violate these guidelines, as do submissions prepared with the help of an outside "tutor".

You should take precautions to protect the confidentiality of your work: preserve the secrecy of your password, do not make files or directories sharable, pick up your printouts promptly and dispose of printouts where they will not tempt other students. All work should be done either in the class directory of your ITD account (preferred) or in your "priv" directory (only if you do not have a class directory).

All submissions should include a comment statement near the top of the program of the form:

THIS CODE IS MY OWN WORK, IT WAS WRITTEN WITHOUT CONSULTING A TUTOR OR CODE WRITTEN BY OTHER STUDENTS - your name

Cases of apparent plagiarism or collusion will be referred to the Honor Council.