#include "Sim.h"
int simnet()
{
	Signal Q00(1, "Q00");
	Signal Out31(1, "Out31");
	Signal Set2(1, "Set2");
	Signal Q21(1, "Q21");
	Signal Load1(1, "Load1");
	Signal Q01(1, "Q01");
	Signal selmem2(1, "selmem2");
	Signal CPU0(1, "CPU0");
	Signal CPU2(1, "CPU2");
	Signal Out11(1, "Out11");
	Signal clk_byte3(1, "clk_byte3");
	Signal Q20(1, "Q20");
	Signal Q11(1, "Q11");
	Signal Load3(1, "Load3");
	Signal Out0(1, "Out0");
	Signal Clear1(1, "Clear1");
	Signal RW(1, "RW");
	Signal Clear3(1, "Clear3");
	Signal Q31(1, "Q31");
	Signal NLoad1(1, "NLoad1");
	Signal NLoad(1, "NLoad");
	Signal Out01(1, "Out01");
	Signal Set1(1, "Set1");
	Signal Out13(1, "Out13");
	Signal Out22(1, "Out22");
	Signal Out1(1, "Out1");
	Signal Out20(1, "Out20");
	Signal Addr1(1, "Addr1");
	Signal Data0(1, "Data0");
	Signal Out23(1, "Out23");
	Signal Load(1, "Load");
	Signal Read(1, "Read");
	Signal clk_byte0(1, "clk_byte0");
	Signal Set3(1, "Set3");
	Signal Q03(1, "Q03");
	Signal Clear0(1, "Clear0");
	Signal Load0(1, "Load0");
	Signal Out21(1, "Out21");
	Signal selmem0(1, "selmem0");
	Signal Clear2(1, "Clear2");
	Signal Data2(1, "Data2");
	Signal Out12(1, "Out12");
	Signal NLoad3(1, "NLoad3");
	Signal Out00(1, "Out00");
	Signal clk_byte2(1, "clk_byte2");
	Signal CPU1(1, "CPU1");
	Signal Load2(1, "Load2");
	Signal Q10(1, "Q10");
	Signal Q23(1, "Q23");
	Signal Out03(1, "Out03");
	Signal selmem3(1, "selmem3");
	Signal clk_byte1(1, "clk_byte1");
	Signal clk_cpu(1, "clk_cpu");
	Signal EN(1, "EN");
	Signal NLoad2(1, "NLoad2");
	Signal Addr0(1, "Addr0");
	Signal Out33(1, "Out33");
	Signal Q02(1, "Q02");
	Signal Data1(1, "Data1");
	Signal Q12(1, "Q12");
	Signal NLoad0(1, "NLoad0");
	Signal Set0(1, "Set0");
	Signal selmem1(1, "selmem1");
	Signal Out32(1, "Out32");
	Signal Out10(1, "Out10");
	Signal Q13(1, "Q13");
	Signal Out02(1, "Out02");
	Signal Data3(1, "Data3");
	Signal Out30(1, "Out30");
	Signal CPU3(1, "CPU3");
	Signal Out2(1, "Out2");
	Signal Q32(1, "Q32");
	Signal NRW(1, "NRW");
	Signal Out3(1, "Out3");
	Signal Write(1, "Write");
	Signal Q33(1, "Q33");
	Signal Q30(1, "Q30");
	Signal Q22(1, "Q22");
	Switch ("ca", Load, '0', Zero);
	Not ("cb", Load, NLoad);
	Nor ("cb", (NLoad, Load0), Clear0);
	Nor ("cb", (NLoad, Load1), Clear1);
	Nor ("db", (NLoad, Load2), Clear2);
	Nor ("db", (NLoad, Load3), Clear3);
	Not ("eb", Load0, NLoad0);
	Not ("eb", Load1, NLoad1);
	Not ("fb", Load2, NLoad2);
	Not ("fb", Load3, NLoad3);
	Nor ("gb", (NLoad, NLoad0), Set0);
	Nor ("gb", (NLoad, NLoad1), Set1);
	Nor ("hb", (NLoad, NLoad2), Set2);
	Nor ("hb", (NLoad, NLoad3), Set3);
	Switch ("af", Load0, '4', Zero);
	Switch ("ae", Load1, '3', Zero);
	Switch ("ad", Load2, '2', Zero);
	Switch ("ac", Load3, '1', Zero);
	Switch ("da", clk_cpu, '5', Zero);
	Dff ("dc", (Set3, Data3, clk_cpu, Clear3),CPU3);
	Dff ("dd", (Set2, Data2, clk_cpu, Clear2),CPU2);
	Dff ("de", (Set1, Data1, clk_cpu, Clear1),CPU1);
	Dff ("df", (Set0, Data0, clk_cpu, Clear0),CPU0);
	Probe ("cc", CPU3);
	Probe ("cd", CPU2);
	Probe ("ce", CPU1);
	Probe ("cf", CPU0);
	Tsb ("ef", CPU3, NRW, Data3);
	Tsb ("ee", CPU2, NRW, Data2);
	Tsb ("ed", CPU1, NRW, Data1);
	Tsb ("ec", CPU0, NRW, Data0);
	Probe ("di", Data3);
	Probe ("dj", Data2);
	Probe ("dk", Data1);
	Probe ("dl", Data0);
	Switch ("sa", Addr0, '6', Zero);
	Switch ("ra", Addr1, '7', Zero);
	Switch ("ya", RW, '8', Zero);
	Switch ("za", EN, '9', Zero);
	Not ("zd", RW, NRW);
	And ("zd", (RW, EN), Read);
	Probe ("yd", Read);
	And ("ze", (NRW, EN), Write);
	Probe ("ye", Write);
	Decoder ("hd-vd", One, (Addr1, Addr0), (selmem3, selmem2, selmem1, selmem0));
	Probe ("ie", selmem3);
	And ("if", (selmem3, Write), clk_byte3);
	Probe ("ig", clk_byte3);
	Probe ("me", selmem2);
	And ("mf", (selmem2, Write), clk_byte2);
	Probe ("mg", clk_byte2);
	Probe ("qe", selmem1);
	And ("qf", (selmem1, Write), clk_byte1);
	Probe ("qg", clk_byte1);
	Probe ("ue", selmem0);
	And ("uf", (selmem0, Write), clk_byte0);
	Probe ("ug", clk_byte0);
	Probe ("gi", Q33);
	Dff ("hi", (Zero, Data3, clk_byte3, Zero),Q33);
	And ("ii", (selmem3, Q33), Out33);
	Probe ("gj", Q32);
	Dff ("hj", (Zero, Data2, clk_byte3, Zero),Q32);
	And ("ij", (selmem3, Q32), Out32);
	Probe ("gk", Q31);
	Dff ("hk", (Zero, Data1, clk_byte3, Zero),Q31);
	And ("ik", (selmem3, Q31), Out31);
	Probe ("gl", Q30);
	Dff ("hl", (Zero, Data0, clk_byte3, Zero),Q30);
	And ("il", (selmem3, Q30), Out30);
	Probe ("ki", Q23);
	Dff ("li", (Zero, Data3, clk_byte2, Zero),Q23);
	And ("mi", (selmem2, Q23), Out23);
	Probe ("kj", Q22);
	Dff ("lj", (Zero, Data2, clk_byte2, Zero),Q22);
	And ("mj", (selmem2, Q22), Out22);
	Probe ("kk", Q21);
	Dff ("lk", (Zero, Data1, clk_byte2, Zero),Q21);
	And ("mk", (selmem2, Q21), Out21);
	Probe ("kl", Q20);
	Dff ("ll", (Zero, Data0, clk_byte2, Zero),Q20);
	And ("ml", (selmem2, Q20), Out20);
	Probe ("oi", Q13);
	Dff ("pi", (Zero, Data3, clk_byte1, Zero),Q13);
	And ("qi", (selmem1, Q13), Out13);
	Probe ("oj", Q12);
	Dff ("pj", (Zero, Data2, clk_byte1, Zero),Q12);
	And ("qj", (selmem1, Q12), Out12);
	Probe ("ok", Q11);
	Dff ("pk", (Zero, Data1, clk_byte1, Zero),Q11);
	And ("qk", (selmem1, Q11), Out11);
	Probe ("ol", Q10);
	Dff ("pl", (Zero, Data0, clk_byte1, Zero),Q10);
	And ("ql", (selmem1, Q10), Out10);
	Probe ("si", Q03);
	Dff ("ti", (Zero, Data3, clk_byte0, Zero),Q03);
	And ("ui", (selmem0, Q03), Out03);
	Probe ("sj", Q02);
	Dff ("tj", (Zero, Data2, clk_byte0, Zero),Q02);
	And ("uj", (selmem0, Q02), Out02);
	Probe ("sk", Q01);
	Dff ("tk", (Zero, Data1, clk_byte0, Zero),Q01);
	And ("uk", (selmem0, Q01), Out01);
	Probe ("sl", Q00);
	Dff ("tl", (Zero, Data0, clk_byte0, Zero),Q00);
	And ("ul", (selmem0, Q00), Out00);
	Or ("wl", (Out00, Out10, Out20, Out30), Out0);
	Or ("wk", (Out01, Out11, Out21, Out31), Out1);
	Or ("wj", (Out02, Out12, Out22, Out32), Out2);
	Or ("wi", (Out03, Out13, Out23, Out33), Out3);
	Tsb ("wl", Out0, Read, Data0);
	Tsb ("wk", Out1, Read, Data1);
	Tsb ("wj", Out2, Read, Data2);
	Tsb ("wi", Out3, Read, Data3);
}