#include "Sim.h"
void Full_Adder (const SD &coord, const Signal &CarryIn, const Signal &a, const Signal &b, const Signal &CarryOut, const Signal &Sum);

void One_Bit_ALU (const SD &coord, const Signal &a, const Signal &b, const Signal &c_in, const Signal &s, const Signal &z, const Signal &c_out);

void Full_Adder (const SD &coord, const Signal &CarryIn, const Signal &a, const Signal &b, const Signal &CarryOut, const Signal &Sum)
{
	Module( coord, "Full_Adder", (CarryIn, a, b), (CarryOut, Sum) );
	Signal z(1, "z");
	Signal y(1, "y");
	Signal x(1, "x");
	Xor ( SD(coord, "aa"), (a, b), x);
	Xor ( SD(coord, "ab"), (x, CarryIn), Sum);
	And ( SD(coord, "bb"), (a, b), y);
	And ( SD(coord, "cb"), (CarryIn, x), z);
	Or ( SD(coord, "bc-cc"), (y, z), CarryOut);
}
void One_Bit_ALU (const SD &coord, const Signal &a, const Signal &b, const Signal &c_in, const Signal &s, const Signal &z, const Signal &c_out)
{
	Module( coord, "One_Bit_ALU", (a, b, c_in, s), (z, c_out) );
	Signal Out_And(1, "Out_And");
	Signal Out_Sum1(1, "Out_Sum1");
	Signal Out_And1(1, "Out_And1");
	Signal l2(1, "l2");
	Signal l0(1, "l0");
	Signal l3(1, "l3");
	Signal Out_Or(1, "Out_Or");
	Signal Out_Or1(1, "Out_Or1");
	Signal Out_Not1(1, "Out_Not1");
	Signal Out_Not(1, "Out_Not");
	Signal l1(1, "l1");
	Signal Out_Sum(1, "Out_Sum");
	Signal c_out1(1, "c_out1");
	And ( SD(coord, "1a"), (a, b), Out_And);
	Or ( SD(coord, "1a"), (a, b), Out_Or);
	Not ( SD(coord, "1a"), a, Out_Not);
	Full_Adder( SD(coord, "1a"), (a), (b), (c_in), (c_out1), (Out_Sum));
	Decoder ( SD(coord, "2a"), One, (s[1], s[0]), (l3, l2, l1, l0));
	And ( SD(coord, "2c"), (l3, Out_And), Out_And1);
	And ( SD(coord, "2c"), (l2, Out_Or), Out_Or1);
	And ( SD(coord, "2c"), (l1, Out_Not), Out_Not1);
	And ( SD(coord, "2c"), (l0, Out_Sum), Out_Sum1);
	And ( SD(coord, "2c"), (l0, c_out1), c_out);
	Or ( SD(coord, "2c"), (Out_And1, Out_Or1, Out_Not1, Out_Sum1), z);
}
int simnet()
{
	Signal control0(1, "control0");
	Signal b1(1, "b1");
	Signal a0(1, "a0");
	Signal z2(1, "z2");
	Signal a3(1, "a3");
	Signal c_out(1, "c_out");
	Signal b0(1, "b0");
	Signal z0(1, "z0");
	Signal c2(1, "c2");
	Signal z3(1, "z3");
	Signal c3(1, "c3");
	Signal a2(1, "a2");
	Signal b3(1, "b3");
	Signal z1(1, "z1");
	Signal b2(1, "b2");
	Signal a1(1, "a1");
	Signal c1(1, "c1");
	Signal control1(1, "control1");
	One_Bit_ALU("ch", (a0), (b0), (Zero), (control1, control0), (z0), (c1));
	One_Bit_ALU("cg", (a1), (b1), (c1), (control1, control0), (z1), (c2));
	One_Bit_ALU("cf", (a2), (b2), (c2), (control1, control0), (z2), (c3));
	One_Bit_ALU("ce", (a3), (b3), (c3), (control1, control0), (z3), (c_out));
	Switch ("ae", a0, '0', Zero);
	Switch ("ad", a1, '1', Zero);
	Switch ("ac", a2, '2', Zero);
	Switch ("ab", a3, '3', Zero);
	Switch ("ak", b0, '4', Zero);
	Switch ("aj", b1, '5', Zero);
	Switch ("ai", b2, '6', Zero);
	Switch ("ah", b3, '7', Zero);
	Probe ("ca", c_out);
	Probe ("eh", z0);
	Probe ("eg", z1);
	Probe ("ef", z2);
	Probe ("ee", z3);
	Switch ("ea", control1, '8', Zero);
	Switch ("eb", control0, '9', Zero);
}