• Compare instruction: compares 2 values and set the status flags (N, Z, V, C) according to the compared result

• Branch instruction(s): makes the CPU "jump" to a certain memory location when a ceratin condition is satisfied. And if that condition is not satisfied, the CPU continues execution with the next instruction (the one after the branch instruction).

a branching instruction has one slot (one instruction) delay The cause of this delay is the fact that the SPARC CPU is "pipelined" (more in CS355) to make the SPARC CPU execute instruction faster.

What this means is:

The instruction that immediately follows a branching instruction in the SPARC assembler program is always fetched (and will be executed unless annulled/cancelled)

You can compare this effect with a car that tries to make a turn when it is going at very high speed... the inertia will make it skid forward a little further before it could make the turn. --- So also, a SPARC CPU that is running at extreme speed will not be able to branch to a different location right away - it first picks up one extra instruction (the one following the branching instruction) and then branches to the target address.

To counter this "delayed" branching effect, always insert a nop operation immediate after each breach instruction

• Well.... actually, there is no cmp instruction in SPARC - but hold on... don't panic. There is no "MOVE" instruction in SPARC either; and we did just fine.

• Recall that the "cmp x, y" instruction in M68000 computes the difference "y - x and sets the conditional codes (the N, Z, V, C flags) according to the result of the difference.

• The subtract instruction in SPARC is used to comparing and setting the flags....

• The sub subtract instruction in SPARC performs a subtract operation but does NOT sets the conditional codes.

• The subcc subtract instruction in SPARC performs a subtract operation AND sets the conditional codes.

• So to do compare, you use subcc to subtract the 2 values and store the result in register g0 - recall that register g0 is a read only register and the value in g0 (zero) does not get updated. In the compare operation, we don't want to update any registers, just the conditional codes/flags....

• In summary, to compare 2 values x in r1 and y in r2 (the values must be in registers in SPARC), you use:

  subcc %r1, %r2, %g0 Computes the difference r1 - r2 and set the status flags (N,Z,V,C) according to the outcome of the subtraction The effect is to compare the value in register r1 against the value in r2 Register g0 cannot be updated, so only the N, Z, V, C flags are updated

• Well, although there is no CMP instruction, we can make it "feel" like that SPARC does have one.

  All we need to do is to make the assembler translate

      cmp %r1, %r2  ---->  subcc %r1, %r2, %g0
   

• That's exactly what the SPARC assembler will do. So this "psuedo instruction" will be translated by the SPARC assembler as:

  cmp %r1, %r2 ----> subcc %r1, %r2, %g0

  What that means is you can write "cmp %r1, %r2" in your assembler program !

• Remember that by the "cmp" instruction by itself is not doing much useful things.

  Just like M68000, you will need to follow the "cmp" instruction with a conditional branch/jump instruction ! (discussed now)

  ---

• Effect of a conditional branch
  • There are also 6 conditional branch instructions and they all work the same way. I will discuss one of them in details first, and then the other 5 will be described just briefly.

  • I will use "Branch if LESS THAN" (bl) for the discussion.

        bl   LABEL	If the status flags, at the moment that this
  			instruction is executed, indicates that the
  			cmp operation resulted in a "LESS THAN"
  			condition, the CPU is instruction to "branch"
  			or "jump" to the memory location marked by
  			LABEL. But due to "pipelining" inside
  			the SPARC CPU, the instruction following
  			the bl LABEL instruction will be
  			executed before the CPU can do the branch
  
  			If the status flags indicates the otherwise
  			(i.e., "NOT LESS THAN"), then the CPU will 
  			continue the execution with the next
  			instruction (i.e., the instruction that 
  			follows the bl LABEL instruction)
  

  • Example:

    
          sethi  %hi(A), %l0
          ld     [%l0 + %lo(A)], %l0  // l0 = A
          sethi  %hi(B), %l1
          ld     [%l1 + %lo(A)], %l1  // l1 = B
    
          cmp    %l0, %l1     // Compare l0 (A) against l1 (B)
          bl     L1	          // Branch to location L1 if A < B
          nop                 // Always put a nop after a branch !
          add    %g0, 1, %g0
          ....
          ....
          ....
      L1: add    %g0, 2, %g0
          ....
     

    • If A < B, the "bl L1" instruction will delay one instruction (CPU will execute nop first) and then it will make the CPU jump to the memory location where the "add %g0, 2, %g0" is at, and continue the program execution from that point onward (and it will not return back where it came from).

    • If A >= B, the "bl L1" instruction does nothing at all (condition is false) and the CPU will continue the execution with the nop instruction and then the next instruction "add %g0, 1, %g0"

  ---

• VERY IMPORTANT NOTE:

  Be very careful with the order of the operands in CMP !

  The meaning of the jump is changed if you flip the operands:

  Notice also that the meaning of the cmp instruction in SPARC and M68000 is "opposite" (because the operands are swapped in the subtract operation).

        M68000			SPARC
        ============		==============
        cmp.L  x, y	        cmp  x, y
        blt    L1			bl   L1
          -- Branch to L1 if	 -- Branch to L1 if
  	-- y < x		 -- x < y
   

• The reason is clear when you realise that:

        M68000			SPARC
        ============		==============
        cmp.L  x, y	        cmp  x, y
  
        computes: y - x           computes: x - y
   

  ---

• Here is the list of all 6 conditional branches in SPARC:
  • be: branch if condition flags indicate last CMP instruction resulted in the equal condition (this one is easy: the Z flag is set !)

  • bne: branch if condition flags indicate last CMP instruction resulted in the not equal condition (this one is easy too: the Z flag is reset !)

  • bl: branch if condition flags indicate last CMP instruction resulted in the less than condition

  • ble: branch if condition flags indicate last CMP instruction resulted in the less than or equal condition

  • bg: branch if condition flags indicate last CMP instruction resulted in the greater than condition

  • bge: branch if condition flags indicate last CMP instruction resulted in the greater than or equal condition

• And then there is one unconditional branch instruction in M68000:
  • ba: branch always (a sure branch)

• You know all there is to know about assembler instructions to construct "if", "if-else", "while", "for" and "do-while" control statements in any high level programming language.

  And if you understood the techniques for if, if-else, while, and for-statements for M68000, you will find the next few pages very boring....

  We will examine each control statement for SPARC again with the same examples as in M68000...