Details of the Instruction Execution Cycle explained with diagrams

An arbitrary state to illustrate the Instruction Execution Cycle

For a concrete example of the Instruction Execution Cycle, let's consider the computer system in some arbitrary state:

The state above depicts the values that are present in the relevant registers when the CPU starts the Instruction Execution Cycle.

Here are the important information that is given by the CPU state

There are some value in the registers of the CPU and these value are arbitrary -- meaning: you can replace all or any one of them with a different value and the example will remain valid.

The values in the registers are actually binary numbers; but for convenience, I am using their decimal equivalence (remember that you can assign a decimal value to a binary number d_nd_n-1...d₁d₀ using the formula: d_n×2ⁿ + d_n
-1×2^n-1 ... + d₁×2¹ + d₀×2⁰)

The following explains the state information in the above diagram:

The PC (= Program Counter) register contains the value 44

That means the next instruction is located at address 44 in the memory
If you look at the memory in the above diagram, you will see that at address 44, the memory contains the instruction "add R2, R0, R1" -- this is the next instruction that the CPU will fetch and execute !!!
In the example, we assume that the instruction code for the instruction "add R2, R0, R1" is represented by 4 bytes --- these 4 bytes are filled with the green color in the diagram.
The instruction "add R2, R0, R1" means: R2 = R0 + R1 (i.e.: add the values in registers R0 and R1 and store the sum in the register R2).

BTW:

The instruction that physically follows the instruction at address 44 is the instruction at address 48 which is represented by the 4 cyan rectangles (bytes) in memory
Remember that in the normal (in-order) control flow case, the CPU fetches and executes instructions that physically follows each other

The IR (= Instruction Register) register contains the previous instruction that just has been executed

Explanation:

We have assumed that the state is at the start of an Instruction Execution Cycle....
Therefore: we have just ended the previous Instruction Execution Cycle (because the CPU go through these cycles repeatedly - when one cycle ends, the new one start immediately !!!)
Since we have ended an Instruction Execution Cycle, the instruction in the IR register has just been executed !!

BTW: we don't need the instruction in the IR any more and we don't care what that instruction was. So the IR is filled with 4 blank boxes that represents the "previous instruction".

As you will see in the example later, the instruction in the IR will be over-written

The PSR (Processor Status Register) contains some arbitrary value denoted by xxx.
This value will not be important in understanding the Instruction Execution Cycle
The registers R0, R1, R2 will be important because the next instruction that the CPU will execute will use them as input and output
You can see in the diagram that currently:
Again, I used the decimal notation because it's convenient -- in reality, these registers contains binary numbers

Slideshow:

(Initial state: PC = 44 (bin !), R0,R1,R2 has initial values. CPU just finished executing the instruction in IR)

(Instruction Fetch: CPU sends PC on address bus and issues READ command)

(Instruction Fetch: in response, memory sends content at address (= instruction "add R2,R0,R1") to CPU)

(Instruction fetch: CPU stores the data (= instruction "add R2,R0,R1") in the IR register)

(CPU increments PC to point to new next instruction - Instruction Fetch step ends)

(Instruction Decode: CPU decodes the instruction inside IR. - see CS355 for hardware details)

(Operands Fetch: IR sends out signals to Registers to direct the selected registers (R0,R1) into input of the ALU)

(Execute: IR sends out signals to ALU to perform the selected operation (add) and sends result (sum) to selected destination register (R2)

(When result (sum) is written to selected destination register (R2), instruction execution cylce is complete !!)

(Start of a NEW execution cycle: CPU fetch instruction from memory at address in PC. Note that PC has a NEW value !!!)

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The Instruction Execution Cycle illustrated by diagram

The Instruction Fetch step will fetch the instruction located at the address given in the PC register (which is the instruction at memory location 44) and store it in the IR register.

The following diagrams show what happens inside the computer system when it performs the Instruction Fetch step:

The CPU first sends out the value of PC on the address bus and the READ signal on the control bus to the memory:

The signals on the address and control buses represents the "send back the data in memory location 44" command to the memory

In response to this command, the memory will send out the content in its memory location 44 on the data bus (wires):

The CPU will then copy the data on the data bus into its IR register (because the CPU is fetching an instruction, it will store the data in its proper place - which is the IR register):

Finally, the CPU updates its PC register to the address of the subsequent instruction (which is 44+4 = 48):

This completes the Instruction Fetch step.

You can see in the diagram that:

The instruction has been fetched and stored in the IR register
The PC register now contains the address (location) of a new next instruction - so if the CPU repeats the steps, the CPU will fetch a different instruction !!!

The CPU will continue with the other steps of the Instruction Execution Cycle to execute (= perform the calculation) specified by the fetched instruction

During the Instruction Decode step, the CPU will determine what the instruction inside the IR register tells it to do.
In this example, we used the instruction "add R2,R0,R1"
In a, the IR register contains a binary number and the CPU has to find out what the binary number represent.
The details of this step will be explained in CS355,
For CS255, we just assume that the CPU has discovered that the instruction in the IR register tells the CPU to add the values in register R0 and R1 and store the sum in register R2.
After the CPU has determined what the instruction tells it to do, the CPU will fetch the operands first.
During the Operand Fetch step, the CPU sends out control (electrical) signals to the appropriate registers to tell these registers to send their values to the input of the ALU circuit:
The IR register will emit control signals to tell the ALU circuit to perform an addition on the input values
The sum is then transmitted to the registers
The IR register will send control signals to register R2 to store the sum:
The result is:
The Instruction Exection Cycle is now completed and the CPU will repeat the cycle all over again...

Postscript

Remember that the CPU will go through the Instruction Execution Cycle ad infinitum (i.e., forever !)

Let's take a look at the state of the CPU after finishing the Instruction Execution Cycle:

What this state is telling us is:

The CPU will fetch and execute the next instruction at memory location 48
When this instruction is fetched, it will over-write the "add R2,R0,R1" instruction in the IR register (because the "add R2,R0,R1" has been executed and is no longer needed)
You can see that when the CPU repeats the Instruction Execution Cycle, it will fetch and execute a different instruction (due to the fact that the CPU updates the PC register after fetching an instruction)