What causes an out-of-order program flow ?

Some instructions executed by the CPU can result in out-of-order program flow

Example instruction that result in in-order program flow:   mov pc, #4 instruction
     (This instruction stores the value 4 into the PC register)

We will examine the instruction execution cycle when the next instruction execute is mov pc, #4

Initial situation:

Comment:
     PC = 44 (see figure)
     So the next instruction is located at memory address 44
     We assume that computer instructions are 4 bytes long
     The picture shows that the 4 bytes at memory location 44 contains the instruction mov pc, #4

How the CPU completes Phase 1, the instruction fetch step: (just like before !!)

The CPU sends:
     A Read command on the control bus
     The value in the PC (= 44) on the address bus

These signals will tell the memory to return the data in its location 44

How the CPU completes Phase 1, the instruction fetch step:

In response, the memory will send the data stored in location 44 onto the databus
     * This data is the next instruction that the CPU wants to execute !!!

How the CPU completes Phase 1, the instruction fetch step:

The CPU will capture the data and store it in the Instruction Register

How the CPU completes Phase 1, the instruction fetch step:

Finally: the CPU will increase the PC by 4 (instruction size) to point to the (new) next instruction

Situation after Phase 1, the instruction fetch step:

(1) The CPU has fetched the current instruction into the Instruction Register (IR)
       * The remainder of the instruction execution cycle are used to process the current instruction !!!

(2) The PC has been update and now points to the next instruction of the next instruction execution cycle
       * This implements the (default) in order program flow execution ordering !!!

How the CPU completes Phase 2, the instruction decode step:

This material is discussed in CS355 - please take that course if you want to know the details...

All that you need to know for CS255 is:
      The CPU now know what operation it needs to perform and with which operands

How the CPU completes Phase 3, the operand fetch step: (same as before !!)

The CPU sends control signals to the specific registers and fetch their values to the input of the ALU

How the CPU completes Phase 4, the instruction execution step:

The CPU instructs the ALU to the pass on the input value and then store the result in the specified (destination) register (PC)

The PC register now points to the memory location 4 !!!

Situation at the end of Phase 4, the instruction execution step:

The CPU has finished executing the instruction add R2, R0, R1 !!!
      (The CPU has added the values in R0 and R1; and stored the result in register R2 !!!)

The instruction execution cycle has ended !!
      (And a new instruction execution cycle will begin immediately !!)

Initial situation of the new instruction execution cycle:

Comment:
     PC = 4 (see figure)
     So the next instruction is located at memory address 4
     The CPU will execute the "new" next instruction out-of-order !!!

We call this behavior "branching" in assembler programming