Review of information important to the 2 examples of the Instruction Execution Cycle

Review:

  • The CPU fetch an instruction and then execute the (fetched) instruction

    The CPU does this repeatedly (i.e.: indefinitely)

  • In-order program flow:

      • The next instruction fetched and executed is the instruction that physically follows the current instruction (that was executed)

  • Out-of-order program flow:

      • The next instruction fetched and executed is the instruction that does not physically follow the current instruction (that was executed)

In this webpage, I will show an example of an in-order program flow instruction execution

Example Instruction with in-order program flow

Example instruction that has an in-order program flow execution: the add instruction

  • Computer instruction: 

        add R2, R0, R1      // R2 := R0 + R1

    The effect of the instruction:

      • add R2, R0, R1 instructs the CPU to add the values in its registers R0 and R1 and store the sum (R0 + R1) in its register R2.

      • After executing the "add R2, R0, R1" instruction, the CPU will fetch (and execute) the instruction that physically follows the "add R2, R0, R1" in memory

Note:   the default behavior of computer instructions is in-order the program flow execution !!

Execution the add R2, R0, R1 (in-order program flow) instruction

The initial situation:

The CPU has (just) finished executing the instruction in the IR register

The CPU must now fetch (and execute) the next instruction -- (assume 1 instruction is 4 bytes long)

Execution the add R2, R0, R1 (in-order program flow) instruction

The initial situation:

Notice that:   Program Counter (PC) = 44

Therefore: the next instruction (4 bytes) is fetched from memory address 44

Execution the add R2, R0, R1 (in-order program flow) instruction

Step 1: the instruction fetch step

The CPU sends the value of its PC on the address bus (to read memory address 44)

The CPU also sends a READ command on the control bus to the memory

Execution the add R2, R0, R1 (in-order program flow) instruction

Step 1: the instruction fetch step (continued)

In response, the memory will send the data in memory address 44 on the data bus

The data on the data bus is the binary code of the next instruction that the CPU must execute !!!

Execution the add R2, R0, R1 (in-order program flow) instruction

Step 1: the instruction fetch step (almost final)

The CPU will store the data on the data bus in its Instruction Register

Result:   the CPU has fetched the next instruction....     but:   the CPU still needs to do one more thing....

Execution the add R2, R0, R1 (in-order program flow) instruction

Step 1: the instruction fetch final step

Increased the Program Counter to the address of the "new" next instruction

Because we assumed that an instruction is 4 bytes long, PC will be increased by 4

Execution the add R2, R0, R1 (in-order program flow) instruction

Taking stock:   what has been achieved by the Instruction Fetch step

(1) The CPU has fetched an (next) instruction into the Instruction Register (IR)

(2) The PC points to the new "next instruction" (i.e.: the CPU has prepared for the next instruction exec cycle)

Execution the add R2, R0, R1 (in-order program flow) instruction

Step 2: the instruction decode step

In the instruction decode step, the CPU determines what operation it needs to perform

The details of the instruction decode step is explained in CS355...

Execution the add R2, R0, R1 (in-order program flow) instruction

Step 3: the operand fetch step

The CPU will transfer the data in the required registers (R0 and R1) to input of the ALU

The ALU contains arithmetic/logc circuitry and will perform the addition operation on the inputs

Execution the add R2, R0, R1 (in-order program flow) instruction

Step 4: the instruction execute step

The CPU will transfer the result of the ALU operation (= R0 + R1) into the destination register R3.

Note:   the instruction add R2,R0,R1 has now been executed by the CPU !!

Execution the add R2, R0, R1 (in-order program flow) instruction

Taking stock :   what exactly have been achieved by the instruction execution cycle

(1) The CPU has fetched and execute the "next" instruction which was add R2,R0,R1

      The effect of the execution was updating register R2 with the sum R0+R1

Execution the add R2, R0, R1 (in-order program flow) instruction

Taking stock :   what exactly have been achieved by the instruction execution cycle

(2) The CPU has has updated the PC to the address of the "new" next instruction

      This "new" next instruction will be fetched and executed by the next instruction exec cycle !!!