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Macros used in makefiles

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• The Macros section
  • Recal the structure of a makefile:

    # Comment lines can appear anywhere Macros section (will be discussed later) Rules section

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  • Macros section:

    Contains zero or more macro definition(s)

    We will now discuss macros...

    (You have seen the rules section)

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• Macros
  • Macro:

    Macro = a pattern that can be expanded into a (usually) larger number of patterns In other words: Macro = an abbreviated representation of a (usually larger) set of instructions

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  • Syntax of a macro definition in makefile:

    src-pattern = replacement-pattern

    Meaning:

    When the pattern $(src-pattern) is found inside a rule of a makefile, it will be replaced with the pattern: replacement-pattern

    Purpose:

    Macros can enhance the flexibility of the rules inside a makefile

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• Example using macros: using different compilers
  • Fact:

    There are many different C compilers. Examples: GNU compiler: gcc Solaris compiler: cc Microsoft C: Visual C++ ... Each C compiler is invoked with a different command name and different command line options

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  • Use macros to adpat a makefile for different C compiler:

    CC=gcc # Compiler command CFLAGS=-c # Compiler options OFLAG=-o # Output flag main: func5a.o func5b.o $(CC) $(OFLAG) main func5a.o func5b.o %.o: %.c func5b.h $(CC) $(CFLAGS) $<

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  • Example Program: (Demo above code)                                                
    • The func5a.c Prog file: click here
    • The func5b.c Prog file: click here
    • The func5b.h header file: click here
    • The Makefile: click here

    How to run the program:

    Right click on link and save in a scratch directory To compile:   gcc xx.c To run:          ./a.out

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  • Change to different platform:

    When you want to compile the C program on a different platform (using a different C compiler), all you need to do is: Update the macro definitions inside the makefile and.... Make.