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Structure of "make files"

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• Structure of a Makefile
  • The format of a Makefile is as follows:

    # Comment lines can appear anywhere Macros section (will be discussed later if time permits) Rules section

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  • Macros section:

    Contains zero or more macro definition(s)

    We will discuss macros later in this webpage

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  • Rule section:

    Contains one or more make rule(s) used to specify file dependency and how to create the target file in the dependency

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• Rules in a Makefile
  • Rules in a Make file:

    A rule will: Specify a target file name Speficy the list of files that the target depends on Specify how to create the target (when one or more of the dependency files is updated)

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  • Syntax of a Make rule:

    targetName : depend-on-file1 depend-on-file2 .... <TAB> UNIX-command-1 # List of commands <TAB> UNIX-command-2 # used to create the ... # target file <TAB> UNIX-command-N

    Explanation:

    The first line of a make rule is the dependeny line and it specifies: The target file name targetName          and      The list of files that the target file depends on: depend-on-file1, depend-on-file2, ... A list of UNIX commands that are used to create the target file when one or more of the depend-on files have be updated Note: The UNIX command must be preceeded by a <TAB> character If a line does not start with a <TAB> character, then Make will consider this to be the end of the make rule

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  • Comment:

    You are responsible for composing (= writing) the commands UNIX-command-1, UNIX-command-2, ... UNIX-command-N that will correctly create the target targetName !!!

  • Example of a make rule:

    hello.o: hello.c # Meaning: target hello.o depends of hello.c <TAB> gcc -c hello.c # Command to keep the target up to date

    Explanation:

    Line 1 hello.o: hello.c specifies that the target file hello.o depends on the file hello.c Line 2: <TAB> gcc -c hello.c tells the Make application to use the UNIX command "gcc -c hello.c" to create the the target file hello when the file hello.c is updated

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• A simple Make file
  • Consider the C program that consists of one single program file:

    File: "hello.c" #include <stdio.h> int main( int argc, char* argv[] ) { printf( "Hello World !\n" ); }

    The file dependencies and maintenance commands were as follows:

    Command: gcc -c hello.c Result: hello.c ----> hello.o Command: gcc -o hello hello.o Result: hello.o ----> hello (executable command in UNIX)

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  • The Make file that represent (= describe) the above dependencies and the actions used to update the targets is as follows:

    hello: hello.o # Meaning: target hello depends of hello.o <TAB> gcc -o hello hello.o # Command to update the target hello hello.o: hello.c # Meaning: target hello.o depends of hello.c <TAB> gcc -c hello.c # Command to update the target hello.o

    Comment:

    You create a Make file using an editor (e.g.: gedit)

    The Make file must be stored in the directory where you store your C program files and header files

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  • I will now show you how to use the make UNIX application program that:

    uses the dependencies specified in a Make file to automatically maintain a C programming project

    The lecture notes in on the next webpage.....