Example:
8 G Bytes of memory, fragmented into 8 modules (banks): Bank 0: addresses 0 - (220 - 1) Bank 1: addresses 220 - (2 * 220 - 1) Bank 2: addresses 2*220 - (3 * 220 - 1) Bank 3: addresses 3*220 - (4 * 220 - 1) Bank 4: addresses 4*220 - (5 * 220 - 1) Bank 5: addresses 5*220 - (6 * 220 - 1) Bank 6: addresses 6*220 - (7 * 220 - 1) Bank 7: addresses 7*220 - (8 * 220 - 1) |
The switching logic circuit will set the switching fabric to route the requests from the input to their destinations.
Setting of the switching control to enable the transmission of the memory addresses from CPU to the memory modules:
The "denied" CPU will get a WAIT signal and will try its request again.
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