The important of the interconnection network between the CPUs and memory banks

  • Each CPU in the multi-processor must fetch its (own) instruction/data from memory:

        

  • The interconnection network between the CPUs and memory banks must be capable to transfer N instructions in 1 bus cycle !!

The properties of the interconnection network

Property 1: the interconnection network must enable any CPU to access any memory bank

 

The properties of the interconnection network

Property 2: when multiple CPUs want to access the same memory bank, only one will succeed:

 

The cross bar interconnection network

A cross bar interconnection network (or switch) connect its inputs to it outputs in a matrix manner:

A connect from an input to an output can be made by activating the correct tri-state-buffer

The cross bar interconnection network

The connection between an input and an output is made when the tri-state-buffer is activated:                                  

A connect from an input to an output can be made by activating the correct tri-state-buffer

How to set the interconnections in the cross bar network

Each CPU sends a memory access request (that contains a memory address):                                  

The switching logic circuit computes a setting of the tri-state-buffers to satisfy the CPU requests

How to set the interconnections in the cross bar network

Example: CPU 0 wants to access memory bank 3, CPU 1 accesses memory bank 1, CPU 2 accesses memory bank 0, and CPU 3 accesses memory bank 2:

The switching logic circuit computes a setting of the tri-state-buffers to satisfy the CPU requests

How to set the interconnections in the cross bar network

Setting for: CPU 0 wants to access memory bank 3, CPU 1 accesses memory bank 1, CPU 2 accesses memory bank 0, and CPU 3 accesses memory bank 2:

The switching logic circuit computes a setting of the tri-state-buffers to satisfy the CPU requests

Conflicting requests

Example: CPU 0 wants to access memory bank 3, CPU 1 accesses memory bank 3, CPU 2 accesses memory bank 0, and CPU 3 accesses memory bank 2:

When multiple CPUs want to access the same memory bank, the requests are conflicting

Conflicting requests

Only ONE request among all the conflicting requests can be granted:                                                        

The unsuccessful CPU(s) will make the (same) request again in the next bus cycle

The non-blocking property

  • An interconnecting network is non-blocking if

      • every non-conflicting requests can always be forwarded (= satisfied) through the interconnecting network

  • The cross bar interconnecting network is non-blocking:

                

Strength and weakness of the cross bar interconnection network
 

  • Strength:

      • The cross bar network is non-blocking

        (It can thus satisfy all non-conflicting requests ---> high performance)

  • Weakness:

      • The switching logic is very complex and does not scale well.

        (The size grows quadractically !!)

        When the number of CPUs (and memory banks) becomes large (e.g., ≥ 1000), the switching logic becomes too complex to make