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Executing a Load instruction

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We now examine in detail how the basic pipeline CPU executes the load instruction.

• Load instruction format
  • Our pipelined CPU can execute 2 types of load instructions:

    ldr r1,[r2 + r3]: Load the word from memory address (location) R2+R3 into register R1. R1 is the destination register ldr r1,[r2 + #N]: Load word from memory address (location) R2+N (N is a constant) into register R1.

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• Recall: Load Instruction Encoding

  Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | D | D | D | x | 0 | Op| Op| x | S | S | S | R | R | R | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ OpCode P: (1 update PSR, 0 do not) ----------------------- I: (1 use Src 2 as constant, 0 reg num) 0 0 Add 0 1 Subtract 1 0 AND 1 1 OR

  Example:

  Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ===> ldr r6,[r3 - r2] (Load content of memory address R3-R2 into reg R6) Dest Reg P OpCode I Src Reg1 Src Reg2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ===> ldr r6,[r3 + #2] (Load content of memory address R3+2 into reg R6)

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• How is the load instruction executed
  • Example:

    ldr r1, [r2 + r3] (Load data from memory addr R2+R3 into reg R1)

    Execution:

    Fetch the operands: Fetch the value of source operand 1 R2 Fetch the value of source operand 2 R3 Compute the memory address: Add: R2 + R3 Access the memory location: Send: R2 + R3 on the address bus (and give MEMREQ and READ signal to memory) Read the data on the data bus (stored in LMDR) Write the fetch value to register: Update the destination register R1 with the value in LMDR

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  Slideshow:

   

  

  (LOAD instruction code and meaning of the bits in instruction)

  

  (Cycle 1: fetch LOAD instruction in ID stage)

  

  (Start of cycle 2: ID stage fetch operands)

  

  (End of cycle 2: operand fetched, instruction advances)

  

  (Start of cycle 3: EX stage computes on operands)

  

  (End of cycle 3: results stored in ALUo (and DMAR) registers, instruction advances)

  

  (Start of cylce 4: MEM stage execute ldr/str/Branch instruction)

  

  (Start of cylce 4: IF stage will ALSO use system bus !!!)

  

  (Start of cylce 4: IF will be stalled (stops its operation) !!!)

  

  (End of cycle 4: MEM stage read data into LDMR, NOP instruction inserted in instruction stream !!!, instruction advances)

  

  (Start of cylce 5: WB stage updates destination register, LOAD instruction select LDMR as source !!!)

  

  (End of cycle 5: destination register updated, instruction discarded)

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• Step 1: Fetch

  • At start of the CPU cycle, the IF stage sends out PC
  • At end of the CPU cycle, the IR(ID) register is updated with the instruction fetched (ldr r1,[r2+r3], R1)

    

  • The picture above depicts the content of the CPU at end of the first CPU cycle (and the start of the 2nd cycle)

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• Step 2: Decode (fetch operands)
  • At start of the CPU cycle, the ID stage sends out selection signal that selects values from R2 (on A bus), R3 (on B bus) and R1 (on D bus).

  • At end of the CPU cycle, the "A" register is updated with R2, the "B" register is updated with R3, "D" register is updated with R1 (but R3 will not be used) and the "IR1" register will contain the constant 3 in the instruction.

  • Also, at the end of the CPU cycle, the instruction (ldr r1,[r2+r3]) is moved into IR(EX) and a new instruction is fetched into IR(ID):

    

  • The picture above depicts the content of the CPU at end of the second CPU cycle (and the start of the 3rd cycle)

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• Step 3: Execute (compute)
  • At start of the CPU cycle, the EX stage selects the "A" register value (= R2) and the "B" register value (= R3) for the ALU, and use the ALU opcode to make ALU add the input values

  • At end of the CPU cycle, ALUo and DMAR registers is updated with the value R2+R3 and SMDR is updated with the value R1 (but the value R1 in SMDR will not be used and discarded - see next step)

  • Also, at the end of the CPU cycle, the instruction (ldr r1,[r2+r3]) is moved into IR(MEM) and a new instruction is fetched into IR(ID):

    

  • The picture above depicts the content of the CPU at end of the 3rd CPU cycle (and the start of the 4th cycle)

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• Step 4: Execute a Memory Access (load/store) or Branch instruction
  • The MEM stage detects that the instruction is a LOAD instruction and will use the system bus to access the memory to perform the load operation

  • Notice that: the IF stage also wants to use the system bus to fetch the next instruction

    The MEM and IF stage cannot share the system bus !!!

  • We must assign priority of using the system bus:

    The MEM stage must be given higher priority !!!

  • Consequence:

    The IF stage must not operate (= fetch instruction) when the MEM stage wants to use the system bus (in the next CPU cycle)

  • We call a stage that is not operating: stalled

  • How to implement stalling:

    A stage operates when it updates its memory elements. So you can stall a stage by not allowing the clock signal to reach the memory elements in the stage by using an AND gate to "block" the clock:

    There are many situations that can cause stalling

    That means that the stall signal is computed to represent all the stalling events

    We must find all possible conflict situations and form the stall signal for each conflicting situation.

    In this example, you see that first situation where you need to stall:

    If ( MEM stage contains a "ldr" instruction ) then Stall IF stage

    We will learn about other conflicting situations very soon (STORE instruction)....

    Graphical representation of the stall situation:

    

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  • Note:

    The LOAD instruction in the MEM stage can affect on the execution of the instruction in the EX stage. I.e.: we may need to stall the EX stage also !!!

    In this example, I will assume that:

    The LOAD instruction in the MEM stage does not affect the outcome of the instruction in the EX stage I.e.:, in this example, I do not require that the EX stage be stalled.

    Later, you will see that you may also need to stall the EX stage when the MEM stage contains a LOAD instruction....

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  • There is a caveat that need to be taken care of:

    The instructions in the ID stage and in the EX stage are moved forward: Normally, the next instruction (from memory) is fetched by the IF stage into the IR(ID) register... However: The IF stage is stalled (= not fetching instruction) and will not fetch the next instruction: Yet, we must put some instruction in IR(ID)...

    Solution:

    We put a "harmless" NOP instruction in IR(ID) !!!

  • This "NOP" instruction insertion is done using a multiplexor in the IF stage:

    The multiplexor has 2 inputs: data bus (instruction from memory) and the hard-coded instruction code for "NOP": When the IF stage is not stalled, the MUX selects the databus input When the IF stage is stalled, the MUX selects the NOP input

    Note: I omit this Mux in many of the figures for simplicity. You must assume that the mux is inside the IF stage in all figures

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  • At the end of the CPU cycle, the LMDR (load memory data register) is updated with the memory value (say 1234) (fetched from address R2+R3), the ALUo1 register is updated with the value R2+R3 (will not be used) and the value in the SMDR register (= R1) is discarded (because SMDR is only used in a STORE instruction)

  • Also, at the end of the CPU cycle, the instruction (ldr r1,[r2+r3]) is moved into IR(WB) and the NOP instruction is fetched into IR(ID)
    

  • The picture above depicts the content of the CPU at end of the 4rd CPU cycle (and the start of the 5th cycle)

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• Step 5: Update register
  • At the start of the CPU cycle, the destination register (= R1) is selected by the Dest field of the IR(WB) and the LOAD instruction code in IR(WR) will select the value in LMDR (= 1234 from memory) for output on the C-bus !!!

    (So the value R2 + R3) in ALUo1 is not used in a LOAD instruction !!)

    Result of the execution of ldr r1,[r2+r3] is:

    

  • At end of the CPU cycle, the register R1 register is updated with the value 1234

  • Also, at the end of the CPU cycle, the instruction (ldr r1,[r2+r3]) is discarded (because we completed the execution !) and a new instruction is fetched into IR(ID)

  • Notice that the NOP instruction will proceed through the pipe, since it does no harm, its only effect is that the CPU "run less fast"...

  • The picture above depicts the content of the CPU at end of the 5rd CPU cycle (and the start of the 6th cycle)

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• Example Program: (Demo above code)                                                

  /home/cs3550001/demo/pipeline/2-ld-instr Executes the following instructions: 10 65 // mov r1, #65 18 10 // mov r2, #10 26 22 // mov r3, #22 34 1 // mov r4, #1 42 8 // mov r5, #8 58 2 // mov r7, #2 0 0 // nop 0 0 // nop 0 0 // nop 0 0 // nop 0 0 // nop 72 19 // ldr r1,[r2+r3] ( R1=memorylocation[R2+R3] ) 0 1 0 1 // Used to show "NOP insertion" by IF stage 0 1 0 1 0 0 0 0 .... 32: 255 254 (11111111 11111110) <--- data loaded into R1)