CS355 Sylabus

Data Hazard in the Basic Pipelining

Not all is well with the basic pipeline...
- Consider the following program that is executed by the basic pipeline:
```
   Assume: R1 = 12, R2=192, R3=48, R4=1, R5=2, R6=3, R7=4

   add r1, r2, r3        // R1 = R2 + R3 
                         // Old value =  12 = 00000000 00001100
                         // New value = 240 = 00000000 11110000 (visually easy to distiguish)
   add r4, r1, r4	 // R4 = R1 + R4
   add r4, r1, r5        // R5 = R1 + R5
   add r4, r1, r6        // R6 = R1 + R6
   add r4, r1, r7        // R7 = R1 + R7
   ...
```
- The correct behavior (one that an assembler programmer would expect) is:
- But that's NOT what will happen in the basic pipelined CPU !!!
Slideshow:

(Cycle 1: fetch "add r1,r2,r3" into ID stage)

(Start of cycle 2: ID stage fetch operands)

(End of cycle 2: operand fetched, instruction advances)

(Start of cycle 3: EX stage computes on operands, ID stage fetches operands)

(End of cycle 3: results stored in ALUo (and DMAR) registers, ID stage fetched wrong r1, all instructions advances)

(Start of cycle 4: MEM stage executes LD/ST/Branch instruction, EX stage computes on (wrong) operands, ID stage fetches (wrong) r1 )

(End of cycle 4: MEM stage does nothing, EX stage computed wrong result, ID stage fetched (wrong) r1 (again), all instructions advances)

(Start of cylce 5: WB stage updates r1, MEM stage execute LD/ST/Branch instruction, EX stage computes on (wrong) operands, will ID stage fetch (wrong) r1 ?? )

(Middle of cycle 5: WB stage updated r1 on rise of clock signal)

(Further in cylce 5: new value of r1 arrives in ID stage)

(End of cycle 5: ID stage fetched new r1 value)

❮ ❯
CPU Cycle 1
- At start of the CPU cycle, the IF stage sends out PC
- At end of the CPU cycle, the IR(ID) register is updated with the instruction fetched (add r1, r2, r3)
- The picture above depicts the content of the CPU at end of the first CPU cycle (and the start of the 2nd cycle)
CPU Cycle 2
- At start of the CPU cycle, the ID stage sends out selection signal that selects values from R2 and R3
- At end of the CPU cycle, A register is updated with R2 = 11, B register is updated with R3= 9.
- Also, at the end of the CPU cycle, the instruction (add r1, r2, r3) is moved into IR(EX) and instruction "add r4, r1, r4" is fetched into IR(ID)
- The picture above depicts the content of the CPU at end of the second CPU cycle (and the start of the 3rd cycle)
CPU Cycle 3
- At start of the CPU cycle, the EX stage selects values from R2 and R3 for the ALU, use the ALU opcode to make ALU add the input values and compute the result 20 (which will be stored in the register R1 later !!!)
  Also, at start of the CPU cycle, the ID stage selects R4 and R1 (!!!) to be copied into the "A" and "B" registers:
- Notice that:
  Therefore: an old (= wrong !!) value 12 of register R1 will be fetched and used in the add r4, r1, r4 instruction execution !!!
- At end of the CPU cycle, ALUo and DMAR registers is updated with the value R1+R2 = 240 (= the future value of R1)
  Also, at the end of the CPU cycle, "A" is updated to R4 (=1) and "B" is updated to the value in R1 (= 12 !!!). This value is a wrong value because R1 should be updated with the new value (= 240) !!
  Also, at the end of the CPU cycle, the instruction (add r1, r2, r3) is moved into IR(MEM), "add r4, r1, r4" is moved into IR(EX) and instruction "add r5, r1, r5" is fetched into IR(ID)
- The picture above depicts the content of the CPU at end of the 3rd CPU cycle (and the start of the 4th cycle)
- We can see that add r4,r1,r4 will be executed incorrectly !!!
CPU Cycle 4
- At start of the CPU cycle, the MEM stage's ALUo1 register will start to receive the output 20 of "add r1, r2, r3".
- Also at start of the CPU cycle, the EX stage selects values from R4 and the old value of R1 for the ALU, use the ALU opcode to make ALU add the input values - the result is INCORRECT because an old value of R1 was used
  Also, at start of the CPU cycle, the ID stage selects R1 and the OLD value of R1 will also be copied into the "B" register (because register R1 has not yet been updated with the new value !!!):
- At end of the CPU cycle, ALUo1 in MEM stage is updated with the value R2+R3 = 240
- Also, at end of the CPU cycle, ALUo and DMAR registers is updated with the value R4+R1(wrong value) = 13 (=1101 bin)
  Also, at the end of the CPU cycle, "A" register is updated to R5 and "B" register is updated to the old (= wrong !) value of R1 .
  Also, at the end of the CPU cycle, the instruction (add r1, r2, r3) is moved into IR(WB), "add r4, r1, r4" is moved into IR(MEM), instruction "add r5, r1, r5" is moved into IR(EX) and instruction "add r6, r1, r6" is fetched into IR(ID)
- The picture above depicts the content of the CPU at end of the 4th CPU cycle (and the start of the 4th cycle)
- We can see that "add r4,r1,r4" and "add r5,r1,r5" will not execute correctly.

CPU Cycle 5

Good news:
Recall that:

D-flipflops used in the pipelined CPU:

The general purpose registers (R1, R2, R3, ..., R7) consist of D-flipflops that are updated when the clock signal goes from 0 -> 1
The "A", "B", "D" registers in the ID-stage consist of D-flipflops that are updated when the clock signal goes from 1 -> 0

Summary:

Now, let's see what will happen when the add r6,r1,r6 instruction is executed
I put the timing in the picture (see the clock signal)
First, at the start of the CPU cycle, the MEM stage's ALUo1 register will receive the output computed value 240 of add r1, r2, r3 instruction:
After half of a cylce - when the clock signal goes from 0 -> 1, the WB stage will update the register R1 with the new value 240:
(because the general purpose registers - of which R1 is one of them - are updated when clock signal goes from 0-->1)
Immediately after R1 is updated, the output of R1 will change from 12 to the correct value 240 and the value 240 will flow from the registers to the input of the "B"-register.
So a little (time) after the midpoint (but before the transition from 1-->0), the new value 240 of R1 will arrive at register B:
Then, at end of the CPU cycle - when the clock signal goes from 1 -> 0 - the "B"-register in the ID-stage will be updated with 240 (= the new (correct) value in R1 !!!):
The picture above depicts the content of the CPU at end of the 5th CPU cycle (and the start of the 6th cycle)
We can see that TWO instructions ("add r4,r1,r4" and "add r5,r1,r5") will not execute correctly. (because they used the old value in register R1 !!!)
The fact that TWO instruction will not be able to obtain the correct value is important in the design of a solution.

Example Program: (Demo above code)

Prog file:

/home/cs355001/demo/pipeline/4a-ALU-hazard Executes this program: 10 12 // mov r1,#12 18 192 // mov r2,#192 26 48 // mov r3,#48 34 1 // mov r4,#1 42 2 // mov r5,#2 50 3 // mov r6,#3 58 4 // mov r7,#4 0 0 // nop 0 0 // nop 0 0 // nop 0 0 // nop 8 19 // add r1,r2,r3 (R1=R2+R3) 32 33 // add r4,r1,r4 (R4 = R1 + R4) ** These instructions 40 41 // add r5,r1,r5 (R5 = R1 + R5) ** will use an old value 48 49 // add r6,r1,r6 (R6 = R1 + R6) 56 57 // add r7,r1,r7 (R7 = R1 + R7)

What to do:

Clock until all stages has 00000000 00000000 for instructions
Then the next instruction fetch is add r1,r2,r3 which will update R1
Next 2 instructions will fetch the wrong value for R1 into the "B"-register (they will fetch the old value 12 = 00000000 00001100)

Now pay attention to the execution of 4th instruction (add r1,r2,r3 is now inside the WB stage):

When clock goes up ⇒ R1 is updated to 00000000 11110000
When clock down ⇒ "B"-register is updated with the correct value in R1 (00000000 11110000)