CS355 Sylabus

Executing a Branch instruction

We now examine in detail how the basic pipeline CPU execute branch instructions

Branch instructions encoding

The branch instruction is encoded differently because branch instructions do not use register operands

The following is the encoding format for branch instructions chosen by Aaron Bush in his honor's project:

Branch condition <-------------- branch offset -----------> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | B | B | B | | | | | | | | | | | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ B B B Branch condition --------------------------------------------------------------- 0 0 0 Branch always 0 0 1 BEQ 0 1 0 BNE 0 1 1 BLT 1 0 0 BLE 1 0 1 BGT 1 1 0 BGE 1 1 1 not used

The first two bit field 11 indicates a branch instruction
The branch condition is coded by the next 3 bits
If the branch is taken (i.e., the jump is made), then the branch offset value is added to the Program Counter (PC)

Example: BRA LABEL

The BLT LABEL (where LABEL is 10 "bytes" away from the current instruction) is encoded as follows:

BRA cond <-------------- Offset -------------------> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ^ ^ | | +-------------------------------------------+ offset = 10

How is a branch instruction executed (= what the CPU must do)

Example:

bra label ^ ... | ... | (32 instructions) ... | v label:
Then, the instruction bra lable is actually translated to: bra 32 (= branch to location PC + 32)

Execution:

Fetch operands:
Add:
This is the target address of the branch instruction.
Update the PC (program counter) with:

Slideshow:

(Branch instruction encoding)

(Cycle 1: fetch branch instruction in ID stage)

(Start of cycle 2: ID stage fetch operands)

(End of cycle 2: operands (PC and offset) fetched, instruction advances)

(Start of cycle 3: EX stage obtains operands and computes branch address)

(End of cycle 3: stored branch address in ALUo (and DMAR) registers, instruction advances)

(Start of cycle 4: MEM stage execute Branch instruction - update PC with branch address !!!)

(End of cylce 4: MEM stage updated PC with branch addres (=label), branch made !!)

(Start of cycle 5: IF stage fetches instruction a memory address label)

(End of cylce 5: IF stage fetched instruction at branch address, bra instr discarded)

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Step 1: Fetch
- At start of the CPU cycle, the IF stage sends out PC
- At end of the CPU cycle, the IR(ID) register is updated with the instruction fetched (BRA LABEL)
- The picture above depicts the content of the CPU at end of the first CPU cycle (and the start of the 2nd cycle)
Step 2: Decode (fetch operands)
- At start of the CPU cycle, the ID stage sends out selection signal that selects value from registers onto the A, B and D buses....
- At end of the CPU cycle, registers A, B and D is updated with some register value (we don't care what values they are, because these registers will not be used by the branch instruction)
- At end of the CPU cycle, registers PC1 is updated with the value in value from the Program Counter (= PC) and IR1 register is updated with the branch offset in the branch instruction (value 32)
- Also, at the end of the CPU cycle, the instruction (BRA LABEL) is moved into IR(EX) and a next instruction (= instr X !!) following the "BRA LABEL" instruction is fetched into IR(ID) (because the CPU has not executed the "BRA LABEL" instruction yet !!!):
- The picture above depicts the content of the CPU at end of the second CPU cycle (and the start of the 3rd cycle)

Step 3: Execute (compute)

At start of the CPU cycle, the branch instruction code (= 00) will make the EX stage selects the value from PC1 as first operand and the value from IR1 as the second operand for the ALU.
The operation performed by the CPU for a branch instruction is always add
At end of the CPU cycle, ALUo and DMAR registers is updated with the value PC+BranchOffset.
Notice that PC + BranchOffset is the branch location (= address) !!!
Clearly, because the BRANCH instruction does use any value in the "A", "B" and "D" registers, fetching (arbitrary) values into the "A", "B" and "D" registers by the branch instruction will not cause any error (harm)....
Also, at the end of the CPU cycle, the instruction (BRA LABEL) is moved into IR(MEM) and another instruction (= instr Y) following the branch instruction is fetched into IR(ID):

The picture above depicts the content of the CPU at end of the 3rd CPU cycle (and the start of the 4th cycle)

Notice that:

The MEM stage was responsible to execute the branch instruction
The figure above shows the control signal emitted by the MEM stage to effectively execute the branch instruction:

Step 4: Execute a Memory Access instruction or a Branch branch

The MEM stage of the basic pipelined CPU will execute the branch instruction.

If the branch is taken, the select hardware in the MEM stage will send out a control signal to the MUX in the IF to direct the ALUo output into PC.

If the branch is not taken (= does not branch), the Select signal will pick the value PC+4

Note:

A real CPU will normally add +4 to the PC to advance to the next instruction because each instruction is 4 bytes long;
In the simulated CPU, the CPU adds +1 to the PC because our memory is "simpler"....

In this case (Branch Always), the ALUo value will be sent to the input of the PC at the start of the 4th step.

At end of the CPU cycle, the PC register is finally updated with the value PC + BranchOffset which is the address of "LABEL" in the branch instruction (the assembler will calculate the offset for you).
Also, at the end of the CPU cycle, the register ALUo1 is updated with PC+Offset. (But as you will see, this value will not be used and no harm will be done.)
And at the end of the CPU cycle, the value R3 in SMDR register is discarded (SMDR register is only used in a STORE instruction - see later)
Also, at the end of the CPU cycle, the instruction (BRA LABEL) is moved into IR(WB) and another instruction (= instr Z) (following the BRA LABEL instruction) is fetched into IR(ID):
The picture above depicts the content of the CPU at end of the 4th CPU cycle (and the start of the 5th cycle)
Notice that PC has now been updated and the next instruction fetched will be the instruction at the label "label", i.e., the program has "finally" made the branch !!!...

Step 5: Update register

The the WB-stage detects a Branch instruction (by checking for 11 in the first 2 bits of the instruction):

The WB stage will block the clock signal to the registers (so the Branch instruction will not update any registers)
(This is the correct behavior, because a branch instruction only updates the program counter (PC))

At the end of the CPU cycle, the instruction (BRA LABEL) is discarded and the instruction at the branch location is fetched into IR(ID)
Notice that THREE instructions following the BRA instruction (instr X, instr Y and instr Z) have been fetched and will be executed by the pipelined CPU !

Example Program: (Demo above code)

/home/cs355001/demo/pipeline/3-bra-instr Executes: 0: 10 62 // mov r1,#62 18 1 // mov r2,#1 26 1 // mov r3,#1 34 1 // mov r4,#1 42 1 // mov r5,#1 50 1 // mov r6,#1 58 1 // mov r7,#1 0 0 // nop 0 0 // nop 0 0 // nop 0 0 // nop 0 0 // nop 12: 192 32 // bra +32 16 10 // add r2,r1,r2 (R2=R1+R2) 24 11 // add r3,r1,r3 (R3=R1+R3) the following 3 instr's will be fetched 32 12 // add r3,r1,r4 (R4=R1+R4) + exec before branch take place 40 13 // add r4,r1,r5 (R4=R1+R4) 48 14 // add r5,r1,r6 (R4=R1+R4) 56 15 // add r6,r1,r7 (R4=R1+R4) 44: 0 1 // <---- bra target 0 2

Watch the value in the Program Counter (upper left hand corner) change to 00000000 00101100 when the branch takes effect

When that happens, the next instruction fetched is: 00000000 00000001 (= address of "label") (in ID:IR, below the PC probes)