CS355 Sylabus

Executing an ALU instruction: Part 1 - Register with Register

We now examine in detail how the basic pipeline CPU execute the 3 different types of instructions.

ALU instructions with 2 register source operands
- Example: add r1,r2,r3 (R1 := R2 + R3)
- The instruction is encoded as follows:
```
            Dest Reg           OpCode   I   Src Reg1    Src Reg2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+  

   =  8 (= first 8 bits in decimal repr) 19 (= second 8 bits in decimal repr)
```
Slideshow:

(Cycle 1: fetch ALU instruction in ID stage)

(Start of cycle 2: ID stage fetch operands)

(End of cycle 2: operand fetched, instruction advances)

(Start of cycle 3: EX stage obtain operands)

(End of cycle 3: results stored in ALUo (and DMAR) registers, instruction advances)

(Start of cylce 4: MEM stage execute LD/ST/Branch instruction)

(End of cycle 4: MEM stage did nothing, instruction advances

(Start of cylce 5: WB stage updates destination register)

(End of cycle 5: destination register updated, instruction discarded)

❮ ❯
Step 1: Fetch
- At start of the CPU cycle, the IF stage sends out PC
- At end of the CPU cycle, the IR(ID) register is updated with the instruction fetched (add r1,r2,r3)
- The picture above depicts the content of the CPU at end of the first CPU cycle (and the start of the 2nd cycle)
Step 2: Decode (fetch operands)
- At start of the CPU cycle, the ID stage sends out selection signal that selects values from R2 (on A bus) and R3 (on B bus) :
  We also use the Destination register number to fetch a register - will be explained later when we discuss the STORE instruction.
- At end of the CPU cycle, the A register is updated with R2, the B register is updated with R3 and D register is updated with R1. (But only registers A and B will actually be used, register D will not be used by the ADD instruction).
- Also, at the end of the CPU cycle, the instruction (add r1,r2,r3) is moved into IR(EX) (= the instruction register in the EX stage) and a new instruction is fetched into IR(ID) (= the instruction register in the ID stage):
- The picture above depicts the content of the CPU at end of the second CPU cycle (and the start of the 3rd cycle)
Step 3: Execute (compute)
- At start of the CPU cycle, the EX stage selects values from the A register (= R2) and the B register (= R3) for the ALU operation, and use the ALU opcode (= 00, "add") to make the ALU add the input values
- At end of the CPU cycle, ALUo and DMAR registers are updated with the value R2+R3 and SMDR register will be updated with the value in the D register (= R3, but R3 will not be used in the "add" operation - see next step).
- Also, at the end of the CPU cycle, the instruction (add r1,r2,r3) is moved into IR(MEM) and a new instruction is fetched into IR(EX):
- The picture above depicts the content of the CPU at end of the 3rd CPU cycle (and the start of the 4th cycle)
Step 4: Memory Access or Branch
- Because the MEM stage of the basic pipelined CPU is used to execute memory access and branch instructions, and "add r1,r2,r3" is neither, there is no processing done by "add r1,r2,r3" in the MEM stage.
  The data in the registers are simply passed to the next stage (= WB stage).
- At end of the CPU cycle, ALUo1 registers is updated with the value R2+R3
- At the end of the CPU cycle, the value R3 in SMDR register is discarded (SMDR register is only used in a STORE instruction - see later)
- Also, at the end of the CPU cycle, the instruction (add r1,r2,r3) is moved into IR(WB) and a new instruction is fetched into IR(MEM):
- The picture above depicts the content of the CPU at end of the 4rd CPU cycle (and the start of the 5th cycle)
Step 5: Write Back - Update register
- At the start of the CPU cycle, the destination register (R1) is selected by the Dest field of the IR(WB) and the value in ALUo1 (= R2 + R3) is selected for output on the C-bus (because the current instruction is an ALU instruction and not a LOAD instruction)
- At end of the CPU cycle, the register R1 register will be updated with the value R2+R3 !!!
- Also, at the end of the CPU cycle, the instruction (add r1,r2,r3) is discarded and a new instruction is fetched into IR(WB):
- The picture above depicts the content of the CPU at end of the 5rd CPU cycle (and the start of the 6th cycle)

Example Program: (Demo above code)

/home/cs355001/demo/pipeline/1a-ALU-instr

Executes the following instructions:

10 65 // mov r1, #65 R1 = 00000000 01000001 18 4 // mov r2, #4 R2 = 00000000 00000100 26 24 // mov r3, #24 R3 = 00000000 00011000 34 2 // mov r4, #2 R4 = 00000000 00000010 42 8 // mov r5, #8 R5 = 00000000 00001000 58 3 // mov r7, #3 R7 = 00000000 00000011 0 0 // nop 0 0 // nop 0 0 // nop 0 0 // nop 0 0 // nop 8 19 // add r1,r2,r3 (R1=R2+R3) R1 := 00000000 00011100