Synchronous bus protocols

  • A synchronous bus protocol is a bus protocol where the progress of the protocol events are pre-planned (with the possibility of delay) using a clock signal

  • Recall what is a clock signal in a computer system:

               

    The protocol steps (events) can be scheduled at any of the moments when the clock signal changes value (from 0 → 1 or from 1 → 0)

  • A motherboard that implements a synchronous bus protocol will contain a wire on the motherboard that carries the clock signal of the bus

  • Overclocking is the phenomenon when the user increased the clock frequency above the recommended clock frequency (to make the bus protocol finish faster)

Illustrating a synchronous protocol using the egg frying example

Steps to fry an egg:

  1. Turning on the stove
  2. Putting a pan on the stove
  3. Poor oil in the pan
  4. Break the egg and put it in the pan
  5. Wait until the egg is cooked
  6. Remove the egg and turn off the stove
 

The synchronous READ protocol
 

Protocol steps exchanged between the CPU and the memory in a READ operation:

 

The synchronous READ protocol
 

In a synchronous protocol, the protocol steps are driven (= scheduled) by a clock signal:

 

The timing diagram of the synchronous READ protocol

The protocol steps are scheduled chronological at the rise or falling edges of the clock:

I will explain the timing diagram in a piece meal manner next....

The timing diagram of the synchronous READ protocol

The signals activated by the CPU and memory when executing the sync READ procotol are:

 

The timing diagram of the synchronous READ protocol

The meaning of the signal transitions in a timing diagram:

 

The timing diagram of the synchronous READ protocol

A (possible) schedule (= timing) of the protocol events using the clock signal:

The timing diagram of the synchronous READ protocol

The signals at The start of an synchronous READ protocol are as follows:

The CPU now starts a READ operation and runs the sync READ protocol...

The timing diagram of the synchronous READ protocol

(1) the CPU sends out the address :

The memory may start working on the request; but it will usually wait till the next step...

The timing diagram of the synchronous READ protocol

(2) the CPU sends out the READ request:

The memory will now fetch the data requested in the READ operation...

The timing diagram of the synchronous READ protocol

(3) the memory will now process the READ request:

The slower working memory will usually asserts the WAIT signal to prevent the CPU from reading invalid data on the data bus. A fast memory do not assert WAIT.

The timing diagram of the synchronous READ protocol

(4) the CPU attempts to read on the falling clock edge and stopped by the WAIT signal:

The CPU will try again at the next falling clock edge !!

The timing diagram of the synchronous READ protocol

(5) the memory finally sends out the data and it also removes (de-asserts) the the WAIT signal:

The Memory is done (it signals that the CPU should read the data on next falling edge !!)

The timing diagram of the synchronous READ protocol

(6) the CPU attempts to READ again, and this time, the CPU succeeds:

Note that the protocol can guarantee that the data on the data bus is correct !!

The timing diagram of the synchronous READ protocol

(7) the CPU must remove (withdraw) the READ request from the bus:

Unlike the asynchronous protocol, the CPU can withdraw all signals (because the memory expects the CPU to finish)

The timing diagram of the synchronous READ protocol

(8) the memory will remove (withdraw) the DATA response from the bus after 1 clock period:

The protocol is finished !!!

The timing diagram of the synchronous READ protocol

Notice that: all signals have returned to their original state !!

Therefore: a new bus cycle can start immediately !!!

Pros and Cons of the Synchronous bus protocol

  • Strength of the Synchronous bus protocol:

    • Simple to implement:

      • The FSM that implements a Synchronous communication protocol uses the bus clock signal to plan out the transitions

  • Weakness of the Synchronous bus protocol:

    • Devices use the same bus clock to plan out state transitions

    • Therefore:

      • Speed differential of devices must be minimized

        I.e.: fast devices do not adapt to slower devices