CS355 Sylabus

Micro Program Flow Control

Before we can discuss the actual micro-program itself, we need to understand how the CPU fetch the next micro-instruction.
Flow control is the flow of program execution. The "normal program execution flow" is sequential, i.e., after executing one instruction, you execute the following one.
Branching alters the "normal program execution flow". You have learned this in CS255.
To understand how the CPU run/execute the micro-porgram, we need to understand how the micro program flow control....
First: where is the micro program ?
Recall that a micro-program is a sequence of micro-instructions that controls the behaviour of the datapath (and thus also the CPU)
Recall also that the CPU has one single purpose: to fetch assembler instructions from memory, decode and execute them.
Therefore, the micro-program is very specific
Normally, programs are stored in the memory. But it would not be practical to store the micro-program in memory because it would be too slow to fetch micro-instructions from memory.
Fortunately, the micro program is very small (because all it does is to instruct the CPU to perform the steps in the assembler instruction execution cycle, which only consists of a few steps).
Thus, the micro-program is stored inside the CPU:
- The micro-program is stored in a ROM (read-only memory). This kind of memory is written once and cannot be changed (You don't ever need to change the mirco-program because the CPU will do the same thing all the time...)
- I want to make sure that you still remember how memory work:
  - The address signals are used to select a row in the memory
  - The bits in the selected row is sent to the output (pins) of the memory
- The ROM containing the micro-program is called the Micro-Instruction ROM (MIR):
Selecting the next micro-instruction
- The address used to select the next micro-instruction is provided by a 8-bit memory called the Micro Program Counter (MPC):

Updating the MPC

The normal program flow is:
The next micro-instruction is found at address MPC + 1
We can update the MPC by MPC + 1 using the following circuit:
Sometimes, we need to branch !!!

The following circuit:

give us the ability to update the MPC to

MPC + 1 or
A specific branch (micro-program) address

How this works:

If we set the branch control signal to set the multiplexor to select the left value (MPC+1), then:

If we set the branch control signal to set the multiplexor to select the right value (branch address), then:

the MPC will be updated to the value of the branch address if the MPC is given a clock
This will cause the micro program to branch to the specified branch address (we branched !!!)

Specifying the branch address
- Every micro-instruction has an 8 bit field that specifies a branch address:
  The last 8 bits in the micro-instruction is a branch address
- These 8 bits are sent to the right side of the 8 multiplexors

The micro-program flow control mechanism, i.e., how is the next micro-instruction selected....

Fetching the next micro-instruction:
The mechanism to determine the next micro-instruction is very similar to how the CPU fetch the next instruction from memory:
- There is a special purpose register called MPC (Micro instruction Program Counter), which contains the address of the next micro-instruction in the micro-program store.
- The next micro-instruction is fetched during phase 1 of the 4-phase clock (you should know this).
- The following figure shows how this is done:
  - MPC sends address selection signal to the micro-instruction store ROM
  - The micro-instruction store ROM outputs the micro-instruction at the given address which are the inputs for the MPC (32 Dffs).
  - Phase 1 of the 4-phase clock will cause the MPC to be loaded with the new micro-instruction
As you should remember, after fetching the micro-instruction (in phase 1), the datapath will fetch the register or MBR operands in phase 2, perform the computation in phase 3 and update the registers in phase 4.
Make a note that: computation is performed in phase 3.
- Thus: the N,Z flags denoting the outcome of the computation are available in phase 3.
Updating MPC - timing:
In assembler programming (in CS255), you have learned to alter the flow of control by using:
- First a COMPARE instruction that test two quantities against each other to set up the flags.
- Then follow the COMPARE instruction with a Conditional Branch instruction.
We could have use the same approach in micro-programming...
Difference is: the compare and updating the MPC is performed by 1 (micro) instruction
As I have emphasized before:
- Thus: the N,Z flags denoting the outcome of the computation are available in phase 3.
Therefore, we can correctly perform a conditional branch operation in phase 4 using the values of the flags !

Thus: the MPC can be updated in phase 4

Possible program control flow:

In assembler programming, here are the possible branches that an instruction can perform:

No branching: the next instruction is the one following the current instruction
Branch always: the next instruction is the one specified by the address in the branch instruction
Conditional branch: depending on the flags, the next instruction can be the one following the current instruction or the one specified by the address in the branch instruction

We want realise all these control flows in micro-programming as well.

Recall from CS255 that the way that the control flow is realised is by updating the program counter:

If PC is updated with PC+1, then:
If PC is updated with the address of the branch location, then:

How to realise all possible control flow in micro-programming:
The following figure shows how the next micro-instruction is selected.
- The field that are relevant in controlling the flow of the micro-program has been "suppressed" so far, so let me introduce them right now:
  - The (branch) conditional codes (2 bits)
  - The Next MPC address (8 bits, which contains the branch address of the branch instruction)
  So every micro-instruction may contain a branch instruction.
- The meaning of the conditional code (is also given in the figure) are as follows:
  - 00 = do not branch
  - 01 = branch on negative
  - 10 = branch on zero
  - 11 = always branch
- This is how micro-program flow control is implemented in hardware:
  - The input of the MPC is connected to the output of a multiplexor
  - This multiplexor has 2 inputs:
    - Input 1 is equal to the current MPC value + 1
    - Input 2 is the branch address in the micro-instruction
  - The datapath will make the multiplexor select the value of MPC + 1 if the micro-instruction does not branch
  - The datapath will make the multiplexor select select the branch address if the micro-instruction performs a branch
  - Phase 4 of the 4-phase clock is the write signal to the MPC register (Dff's).
  The selection signal of the multiplexor is the output of a branch logic circuit. This branch logic circuit will output 0 if no branching is desired and will output 1 if the micro-program will branch.
- The logic table of the branch logic circuit is as follows:
  
  I trust that you all can wire a circuitry that will perform this logic function with little problem by now...
Examples:
- Example 1: The following figure shows a situation where a branch is not taken:
- Example 2: The following figure shows a situation where a branch is taken:
- The figure shows that the current value of MPC = 14
- The micro-instruction's branch condition code = 01 (branch on N = 1)
- The result of the computation is such that N = 1
- Therefore, the branch logic will output 1 and the multiplexor will select the value 32 (the branch address) as output.
- So the value of the branch address is presented as input of the MPC during phase 3 of the 4-phase clock.
- When the 4-phase clock enters phase 4, the MPC register (Dffs) will be updated with the value 32.
- When the 4-phase clock goes back to phase 1, the next instruction that will be fetched is the micro-instruction at location 32 in the micro-instruction store.
- This is the case of branching....
We are almost ready for the the micro-program.... we only need to assign numbers to the registers...